ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 215

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

19.5
8006G–AVR–01/08
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). See
Figure 19-1. Serial Programming and Verify
Note:
After RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase operations can be executed.
Table 19-10. Pin Mapping Serial Programming
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
In
pins dedicated for the internal SPI interface.
Symbol
MOSI
MISO
Figure 19-1
SCK
Table 19-10
above, the pin mapping for SPI programming is listed. Not all parts use the SPI
below.
MOSI
MISO
SCK
ck
ck
Pins
PA6
PA5
PA4
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
RESET
GND
VCC
I/O
O
I
I
+1.8 - 5.5V
ATtiny24/44/84
ck
ck
>= 12 MHz
>= 12 MHz
Description
Serial Data in
Serial Data out
Serial Clock
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