ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 189

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

8006G–AVR–01/08
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 16-6
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high.
Figure 16-7. ADC Timing Diagram, Free Running Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
below. This assures a fixed delay from the trigger event to the start of conversion. In
MUX and REFS
Update
1
Conversion
Complete
2
One Conversion
12
3
Sample &
Hold
4
13
5
14
6
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
9
2
MUX and REFS
Update
10
Conversion
Complete
3
11
ATtiny24/44/84
Sample & Hold
12
4
13
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
2
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