ATA5771 ATMEL Corporation, ATA5771 Datasheet - Page 159

• Manufacturer Part Number: ATA5771
• Manufacturer: ATMEL Corporation

12.11 Register Description
12.11.1
8006G–AVR–01/08
TCCR1A – Timer/Counter1 Control Register A
Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-
dent of the WGM13:0 bits setting.
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 12-2.
and ICF n
Bit
0x2F (0x4F)
Read/Write
Initial Value
COM1A1/COM1B1
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
OCRnx
as TOP)
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
0
0
1
1
COM1A1
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
COM1A0/COM1B0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
0
1
0
1
COM1B1
Table 12-2 on page 107
R/W
5
0
COM1B0
R/W
4
0
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to
low level).
Set OC1A/OC1B on Compare Match (Set output to
high level).
Description
TOP
TOP
R
3
–
0
shows the COM1x1:0 bit functionality
clk_I/O
BOTTOM
R
2
–
0
TOP - 1
ATtiny24/44/84
/8)
New OCRnx Value
WGM11
R/W
1
0
WGM10
BOTTOM + 1
R/W
0
0
TOP - 2
TCCR1A
107