AD1954 Analog Devices, AD1954 Datasheet - Page 19

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

Note that by having interpolation filters in the main channels, but
not the subwoofer channel, there is a potential time-delay mis-
match between the main and sub channels. The group delay of
the digital interpolation filters used in the main left/right channels
is about 0.5 ms. This must be compared to the group delay of
the external analog filter used in the subwoofer path. If the
group delay mismatch causes a frequency response error (when the
two signal are “acoustically added”), then the programmable delay
feature can be used to put extra delay in either the subwoofer path
or the main left/right path.
SPI PORT
Overview
The AD1954 has many different control options. Most signal-
processing parameters are controlled by writing new values to
the parameter RAM using the SPI port. Other functions such as
volume and de-emphasis filtering are programmed by writing to
SPI control registers.
The SPI port uses a four-wire interface, consisting of CLATCH,
CCLK, CDATA and COUT signals. The CLATCH signal
goes LOW at the beginning of a transaction and HIGH at the
end of a transaction. The CCLK signal latches the serial input
data on a LOW-to-HIGH transition. The CDATA signal
carries the serial input data, and the COUT signal is the serial
output data. The COUT signal remains tri-stated until a READ
operation is requested. This allows other SPI-compatible pe-
ripherals to share the same readback line.
The SPI port is capable of full read/write operation for all of the
memories (Parameter and Program) and some of the SPI registers
(Control Register 1 and Data Capture registers). The memories
may be accessed in both a single-address mode or in burst mode.
All SPI transactions follow the same basic format, shown in Table I.
The Wb/R bit is LOW for a write, and HIGH for a read opera-
tion. The 10-bit address word is decoded into either a location
in one of the two memories (Parameter or Program) or one of
the SPI registers. The number of Data bytes varies according to
the register or memory being accessed. In burst-write mode
CLATCH
CDATA
CCLK
CLATCH
CDATA
CCLK
COUT
PRELIMINARY TECHNICAL DATA
BYTE 0
HI-Z
BYTE 0
BYTE 1
DATA
(available for loading the RAMs only), an initial address is given
followed by a continuous sequence of data for consecutive RAM
locations. The detailed data format diagram for continuous-
mode operation is given in SPI Read/Write data formats.
A sample timing diagram for a single SPI WRITE operation to
the parameter RAM is shown in Figure 15.
Byte 0
00000, Wb/R, adr[9:8] Adr[7:0]
A sample timing diagram of a single SPI READ operation is
shown in Figure 16. The COUT pin goes from tri-state to driven
at the beginning of Byte 2. Byte 0 and 1 contain the address
and R/W bit, and bytes 2–4 carry the data. The exact format is
shown in Tables VIII to XIX.
The AD1954 has several mechanisms for updating signal-
processing parameters in real-time without causing loud pops or
clicks. In cases where large blocks of data need to be downloaded,
the DSP core can be shut down, new data loaded, and then re-
started. The shutdown and re-start mechanisms employ a gradual
volume ramp to prevent clicks and pops. In cases where only a
few parameters need to be changed (for example, a single biquad
filter), a “safeload” mechanism is used that allows a block of SPI
registers to be transferred to the parameter RAM within a single
audio frame while the core is running. The safeload mode uses
internal logic to prevent contention between the DSP core and
the SPI port.
SPI Address Decoding
Table II shows the address decoding used in the SPI port. The
SPI address space encompasses a set a registers and two RAMs,
one for holding signal-processing parameters and one for holding
the program instructions. Both of the RAMs are loaded on
power-up from on-board “boot” ROMs.
BYTE 1
DATA
XXX
Table I. SPI Word Format
Byte 1
DATA
BYTE 4
Byte 2 Byte 3 Byte 4
Data
HI-Z
Data
AD1954
Data