AD1954 Analog Devices, AD1954 Datasheet - Page 20

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

AD1954
SPI Address
0–255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
269–510
511
512–1024
Control Register 1
Control Register 1 is an 11-bit register that controls serial modes,
de-emphasis, mute, power-down, and SPI-to-Memory transfers.
Table III documents the contents of this register. Bit <11> controls
the functions of the DEEMP/SDATA_AUX pin. The default
setting is “0” which corresponds to the de-emphasis function. More
information is available in the Pin Functions Section.
The wordlength bits are used in right-justified serial modes to deter-
mine where the MSB is located relative to the start of the audio frame.
The serial mode bits select one of four modes, which are discussed in
the Serial Data Input Port section. The de-emphasis bits turn on the
internal de-emphasis filter for one of three possible sample rates.
The halt program bit is used to initiate a volume ramp-down fol-
lowed by a shutdown of the DSP core. The user may poll for this
operation to complete by reading Bit 1 of Control Register 1.
Soft mute is used to initiate a volume ramp-down sequence. If the
initial volume was set to 1.0, this operation will take 512 audio frames
to complete. When this bit is de-asserted, a “ramp-up” sequence is
Program RAM
Register Name
Parameter RAM
SPI Control Register 1
SPI Control Register 2
Volume Left
Volume Right
Volume Sub
Data Capture (SPI Out) #1
Data Capture (SPI Out) #2
Data Capture (Serial Out) Left
Data Capture (Serial Out) Right
Parameter RAM Safe Load Register 0
Parameter RAM Safe Load Register 1
Parameter RAM Safe Load Register 2
Parameter RAM Safe Load Register 3
Parameter RAM Safe Load Register 4
Unused
Test Register
PRELIMINARY TECHNICAL DATA
Table II. SPI Port Address Decoding
Read/Write wordlength.
Write: 22 Bits
Read: 22 Bits
Write: 11 Bits
Read: 2 Bits
Write: 9 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 22 Bits
Read: N/A
Write: 9 Bit Program counter value, 2 Bit Register Address
Read: 24 Bits
Write: 9 Bit Program Counter Value 2 Bit Register Address
Read: 24 Bits
Write: 9 Bit Program Counter value, 2 Bit Register Address
Read: N/A
Write: 9 Bit Program Counter value, 2 Bit Register Address
Read: N/A
Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data
Read: N/A
Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data
Read: N/A
Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data
Read: N/A
Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data
Read: N/A
Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data
Read: N/A
Write: 8 Bits
Read: N/A
Write: 35 Bits
Read: 35 Bits
initiated until the volume returns to its original setting. The initiate-
safe-transfer bit will request a data transfer from the SPI “safeload”
registers to the parameter RAM. The safeload registers contain
address-data pairs, and only those registers that have been written to
since the last transfer operation will be uploaded. The user may poll
for this operation to complete by reading bit 0 of Control Register 1.
Safeload Mechanism section goes into more detail on this feature.
The soft power down bit stops the internal clocks to the DSP core,
but does not reset the part. The digital power consumption is
reduced to a low level when this bit is asserted. Reset can only be
asserted using the external reset pin.
The Enable-DCSOUT bit is used to turn on the Data Capture
Serial Out pin. This pin may be used to send data that is captured
using the data-capture feature to external devices such as an addi-
tional stereo DAC. The Data Capture Registers section gives more
information about the data capture feature.
When a read operation is performed on Control Register 1, two
bits are returned, as shown in Table IV.