AD1954 Analog Devices, AD1954 Datasheet - Page 25

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

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Options for Parameter Updates
The Parameter and Program RAMs can be written and read
using one of several methods.
1. Direct read/write. This method allows direct access to the
2. Direct read/write after core shutdown. This method avoids
3. “Safeload” writes, where up to five SPI registers are loaded
The default decay time of the hold/release circuit is set fast enough that the decay is dominated by the time constant of the RMS detector.
RAMs. Since the RAMs are also being used during real-time
DSP operation, a glitch will likely occur at the output. This
method is not recommended.
the glitch while accessing the internal RAMs by first shutting
down the core. This is recommended for transferring large
amounts of data, such as initializing the parameter RAM at
power-up, or downloading a completely new program. These
transfers can be sped up by using “burst mode,” where an
initial address followed by blocks of data are sent to the RAM.
with address/data intended for the parameter RAM. The data
is then transferred to the requested address when the RAM is
IIR2 Xover Sub a2
IIR Sub RMS b0
IIR Sub RMS b1
IIR Sub RMS b2
IIR Sub RMS a1
IIR Sub RMS a2
Main Compressor Lookup Table base
Main Compressor attack/RMS time constant
Main Post-Compressor Gain
Subwoofer compressor lookup table base
Sub Compressor attack/RMS time constant
Post-compressor gain (SUB)
High-pass filter cutoff frequency
Main compressor look-ahead delay
Delay Left
Delay Right
Delay Sub
Stereo spreading coefficient
Stereo spreading frequency control
Subwoofer re-injection to main left
Subwoofer re-injection to main right
Subwoofer channel input gain from Left IN
Subwoofer channel input gain from Right IN
Main Detector HOLD time, samples (4095 MAX)
Sub Detector HOLD time, samples (4095 MAX)
Main detector decay time
Sub detector decay time
PRELIMINARY TECHNICAL DATA
The next section discusses these options in more detail.
Soft Shutdown Mechanism
When writing large amounts of data to the program or parameter
RAM, the processor core should be halted to prevent unpleasant
noises from appearing at the audio output. Figure 17 shows a
graphical representation of this mechanism’s volume envelope.
Points A–D are referenced in the following description. Bit 10 in
serial Control Register 0 (processor shutdown bit) will shut
down the processor core. When the processor shutdown bit is
asserted (A), an automatic volume ramp-down sequence (B)
lasting from 10 ms – 20 ms will occur, followed by a shutdown
not busy. This method can be used for dynamic updates
while live program material is playing through the AD1954.
For example, a complete update of one biquad section can
occur in one audio frame, while the RAM is not busy. This
method is not available for writing to the Program RAM or
control registers.
0
1.0
0
0
0
0
1.0 (all)
5.75 × 10
1.0
1.0 (all)
5.75 × 10
1.0
3.92 × 10
0
0
0
0
0
0.112694
0.0
0.0
0.5
0.5
0
0
0.069611 (10000 dB/sec)
0.069611 (10000 dB/sec)
–4
–4
–4
(120 dB/sec)
(120 dB/sec)
AD1954