AD1954 Analog Devices, AD1954 Datasheet - Page 26

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

AD1954
of the core. This method of shutting down the core prevents
pops or clicks from occurring. After the shutdown is complete,
Bit 1 in Control Register 1 will be set. The user can either poll
for this bit to be set, or just wait for a period longer than 20 ms.
Once the core is shut down (C), the parameter or program RAMs
may be written or read freely. To ease the transfer of large blocks
of sequential data, a “block transfer” mode is supported where a
starting address followed by a stream of data is sent to the memory.
The address into the memory will be automatically incremented
for each new write. This mode is documented in the SPI Data
Format section of this datasheet.
Once the data has been written, the shutdown bit can be cleared
(D). The processor then will initiate a volume “ramp-up” sequence
lasting for 10 – 20 ms. Again, this reduces the chance of any pop
or click noise from occurring.
Safeload Mechanism
Many applications require real-time control of filter characteristics,
such as bass/treble controls and parametric or graphic equaliza-
tion. To prevent instability from occurring, all of the parameters
of a particular biquad filter must be updated at the same time;
otherwise, the filter could execute for one or two audio frames
with a mixture of old and new coefficients. This mix of old and
new could cause temporary instability, leading to transients that
could take a long time to decay.
The method used in the AD1954 to eliminate this problem is to
load a set of five registers in the SPI port with the desired param-
eter RAM address and data. Five registers are used because each
Memory
Parameter RAM
Program RAM
Size
256
512
×
×
22
35
SPI Address Range
0 – 255
512 – 1023
A
PRELIMINARY TECHNICAL DATA
B
Table VII. Read/Write Modes
C
Read
YES
YES
Write
YES
YES
biquad filter has five coefficients. Once these registers are loaded,
the “Initiate Safe Transfer” bit in SPI Control Register 1 is set.
Once this bit is set, the processor waits for a period of time in
the program sequence where the parameter RAM is not being
accessed for at least five consecutive instruction cycles. When
the program counter reaches this point, the parameter RAM is
written with five new data values, at addresses corresponding to
those entered in the safeload registers. When the operation is
complete, Bit 0 of Control Register 1 is set. This bit may be
polled by the external microprocessor until a 1 is read. This bit
will be reset on a read operation. The polling operation is not
required; the safeload mechanism guarantees that the transfer
will be complete within one audio frame.
The Safeload logic automatically sends only those Safeload
registers that have been written to since the last Safeload opera-
tion. For example, if only two parameters are to be sent, then it
is only necessary to write to two of the five Safeload registers.
When the Request Safe Transfer bit is asserted, only those two
registers will be sent; the other three registers are not sent, and
can still hold old or invalid data.
The Safeload mechanism is not limited to uploading biquad
coefficients; any set of five values in the parameter RAM may be
updated in the same way. This allows real-time adjustment of
the compressor/limiter, delay, or stereo spreading blocks.
Summary of RAM modes
Table VII shows the sizes and available modes of the Parameter
RAM and the Program RAM.
Burst Mode Available
YES
YES
D
Write Modes
Direct Write, Write after core
shutdown, “Safeload” write
Direct Write, Write after core
shutdown