MT54V512H18A Micron Semiconductor Products, Inc., MT54V512H18A Datasheet - Page 2

• Manufacturer Part Number: MT54V512H18A
• Description: 9Mb QDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
ters controlled by the K or K# input clock rising edges.
Active LOW byte writes (BW0#, BW1#) permit byte
write selection. Write data and byte writes are regis-
tered on the rising edges of both K and K#. The
addressing within each burst of two is fixed and
sequential, beginning with the lowest address and
ending with the highest one. All synchronous data out-
puts pass through output registers controlled by the
rising edges of the output clocks (C and C# if provided,
otherwise K and K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
sramds) for the latest data sheet.
READ/WRITE Operations
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
NOTE:
512K x 18 2.5V V
MT54V512H18A_16_A.fm - Rev 10/02
operation. All synchronous inputs pass through regis-
1. The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing
2. n = 18
D (Data In)
ADDRESS
Depth expansion is accomplished with port selects
Four balls are used to implement JTAG test capabili-
The SRAM operates from a +2.5V power supply, and
Please refer to Micron’s Web site
All bus transactions operate on an uninterruptable
diagramsfor detailed information.
BW0#
BW1#
W#
R#
K#
K#
DD
K
K
, HSTL, QDRb2 SRAM (Footer Desc variable)
W#
18
R#
n
REGISTRY
REGISTRY
ADDRESS
& LOGIC
& LOGIC
DATA
36
n
Functional Block Diagram: 512K x 18
K
(www.micron.com/
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0.16µm Process
D
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Figure 2:
MEMORY
ARRAY
2 x 36
n
2
transactions can remain in operation on both buses
providing that the address rate can be maintained by
the system (2x the clock frequency).
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of K using C and C# as the
output timing references, or using K and K#, if C and
C# are tied HIGH. If C and C# are tied HIGH, they may
not be toggled during device operation. Output tri-
stating is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every K rising edge.
edge. The address for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K which
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and to
provide fully coherent data for all combinations of
READs and WRITEs. A READ can immediately follow a
WRITE even if they are to the same address. Although
the WRITE data has not been written to the memory
array, the SRAM will deliver the data from the write
register instead of using the older data from the mem-
ory array. The latest data is always utilized for all bus
transactions. WRITE cycles can be initiated on every K
rising edge.
READ cycles are pipelined. The request is initiated
WRITE cycles are initiated by W# LOW at K rising
2.5V V
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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36
, HSTL, QDRb2 SRAM
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C,C#
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512K x 18
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©2002, Micron Technology Inc.
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ADVANCE
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18
(Data Out)
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