MT54V512H18A Micron Semiconductor Products, Inc., MT54V512H18A Datasheet - Page 5

• Manufacturer Part Number: MT54V512H18A
• Description: 9Mb QDR SRAM, 2.5V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 3:
512K x 18 2.5V V
MT54V512H18A_16_A.fm - Rev 10/02
SYMBOL
BW0#
BW1#
V
DNU
TDO
TMS
V
TCK
V
W#
TDI
V
ZQ
Q_
DD
SA
R#
K#
C#
D_
K
C
REF
DD
SS
Q
DD
, HSTL, QDRb2 SRAM (Footer Desc variable)
Ball Descriptions
Output
Output
Output
Supply
Supply
Supply
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K for READ cycles and must meet the setup and hold times
around the rising edge of K# for WRITE cycles. See Ball Assignment figures for address
expansion inputs. All transactions operate on a burst of two 18-bit data (one clock period of
bus activity). These inputs are ignored when both ports are deselected.
Synchronous Read: When LOW, this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising edge
of K.
Synchronous Write: When LOW, this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.
Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be
registered and written if W# had initiated a WRITE cycle. These signals must meet setup and
hold times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. BW0# controls D0:D8, and BW1# controls D9:D17. See Ball Assignment
figures for signal to data relationships.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.
Output Clock: This clock pair provides a user-controlled means of tuning device output data.
The rising edge of C is used as the output timing reference for the first output data. The
rising edge of C# is used as the output reference for second output data. Ideally, C# is 180
degrees out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the
output reference clocks instead of having to provide C and C# clocks. If tied HIGH, these
inputs may not be allowed to toggle during device operation.
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left as No Connects
if the JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to V
JTAG function is not used in the circuit.
HSTL Input Reference Voltage: Nominally V
noise margin. Provides a reference voltage for the HSTL input buffer trip point.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor
from this ball to ground. Alternately, this ball can be connected directly to V
enables the minimum impedance mode. This ball cannot be connected directly to GND or left
unconnected.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges
of K and K# during WRITE operations. See Ball Assignment figures for ball site location of
individual signals.
IEEE 1149.1 Test Output: 1.8V I/0 level.
Do Not Use: These balls should not be used.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands.
See Ball Assignment figures for ball site location of individual signals.
Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for
range.
Power Supply: Isolated Output Buffer Supply. Nominally 2.5V. See DC Electrical Characteristics
and Operating Conditions for range.
Power Supply: GND.
0.16µm Process
5
DESCRIPTION
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q/2, but may be adjusted to improve system
DD
, HSTL, QDRb2 SRAM
512K x 18
DD
©2002, Micron Technology Inc.
Q, which
ADVANCE
SS
if the