MT55L128L32P1 Micron Semiconductor Products, Inc., MT55L128L32P1 Datasheet

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MT55L128L32P1

Manufacturer Part Number
MT55L128L32P1
Description
4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet

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4Mb
ZBT
FEATURES
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V ±5% power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• Advanced control logic for minimum control signal
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or interleaved burst modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 8Mb, and
• Automatic power-down
• 165-pin FBGA package
• 100-pin TQFP package
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Package
• Operating Temperature Range
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
supply (V
interface
I/Os and control signals
eliminate the need to control OE#
16Mb ZBT SRAM family
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
3.3V I/O
2.5V I/O
100-pin TQFP
165-pin FBGA
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
256K x 18
128K x 32
128K x 36
256K x 18
128K x 32
128K x 36
®
DD
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
SRAM
Q)
MT55L256L18P1T-10
Part Number Example:
DD
MT55L256L18P1
MT55L128L32P1
MT55L128L36P1
MT55L256V18P1
MT55L128V32P1
MT55L128V36P1
)
MARKING
None
-7.5
-10
F*
IT
-6
T
1
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
3.3V V
* A Part Marking Guide for the FBGA devices can be found on Micron’s
** Industrial temperature range offered in specific speed grades and
GENERAL DESCRIPTION
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
128K x 32, or 128K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
Web
configurations. Contact factory for more information.
The Micron
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
4Mb: 256K x 18, 128K x 32/36
site—http://www.micron.com/support/index.html.
DD
, 3.3V or 2.5V I/O
®
Zero Bus Turnaround
100-Pin TQFP
PIPELINED ZBT SRAM
165-Pin FBGA
1
©2003, Micron Technology, Inc.
(ZBT
®
) SRAM

Related parts for MT55L128L32P1

MT55L128L32P1 Summary of contents

Page 1

... Industrial (-40°C to +85°C)** Part Number Example: MT55L256L18P1T-10 4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 4Mb: 256K x 18, 128K x 32/36 MT55L256L18P1, MT55L256V18P1, MT55L128L32P1, MT55L128V32P1, MT55L128L36P1, MT55L128V36P1 3. MARKING -6 NOTE: 1 ...

Page 2

SA0, SA1, SA MODE CLK K CKE# WRITE ADDRESS REGISTER 1 ADV/LD# BWa# BWb# R/W# OE# CE# CE2 CE2# 17 SA0, SA1, SA MODE CLK K CKE# WRITE ADDRESS REGISTER 1 ADV/LD# BWa# BWb# BWc# BWd# R/W# OE# CE# ...

Page 3

GENERAL DESCRIPTION (continued) The synchronous inputs include all addresses, all data inputs, chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), cycle start input (ADV/LD#), synchronous clock enable (CKE#), byte write enables (BWa#, BWb#, BWc#, and ...

Page 4

TQFP PIN ASSIGNMENT TABLE PIN# x18 x32 x36 PIN# x18 DQc DQc DQc DQc DQc DQc DQc 31 ...

Page 5

NF** 83 NF** 84 ADV/LD# 85 OE# (G#) 86 CKE# 87 R/W# 88 CLK CE2# 92 BWa# 93 BWb CE2 97 CE ...

Page 6

TQFP PIN DESCRIPTIONS x18 x32/x36 32–35, 44–50, 32–35, 44–50, 80–82, 99, 100 81, 82, 99, 100 – 95 – ...

Page 7

TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 88 88 (a) 58, 59, 62, (a) 52, 53, 63, 68, 69, 56–59, 62, 63 72–74 ( 12, 13, (b) 68, 69, 18, 19, 22–24 72–75, 78 6–9, ...

Page 8

CE# BWb# NC CE2# CKE CE2 NC BWa# CLK R/ ...

Page 9

FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R, 4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R, 9P, 9R, 10A, 9P, 9R, 10A, 10B, 10P, 10B, 10P, 10R, 11A, 11R 10R, ...

Page 10

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 8A 8A ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, ...

Page 11

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 4C, 4N, 5C, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, ...

Page 12

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...

Page 13

DS BEGIN READ READ READ BURST BURST READ KEY: COMMAND DS READ WRITE BURST NOTE STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) ...

Page 14

TRUTH TABLE (Notes 5–10) OPERATION DESELECT Cycle DESELECT Cycle DESELECT Cycle CONTINUE DESELECT Cycle READ Cycle (Begin Burst) READ Cycle (Continue Burst) NOP/DUMMY READ (Begin Burst) DUMMY READ (Continue Burst) WRITE Cycle (Begin Burst) WRITE Cycle (Continue Burst) NOP/WRITE ABORT ...

Page 15

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V ........................................ -0. .................................................. -0. Storage Temperature (plastic) ........... ...

Page 16

I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ T ≤ +70° +3.3V ±0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage ...

Page 17

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1) (0°C ≤ T ≤ +70° DESCRIPTION CONDITIONS Device selected; All inputs ≤ V Power Supply or ≥ Cycle time ≥ Current: IH Operating V = MAX; ...

Page 18

TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to ...

Page 19

AC ELECTRICAL CHARACTERISTICS (Notes (0°C ≤ T ≤ +70° DESCRIPTION SYMBOL Clock t Clock cycle time KHKH Clock frequency t Clock HIGH time KHKL t Clock LOW time KLKH Output Times t Clock to output ...

Page 20

I/O AC TEST CONDITIONS Input pulse levels ................................... V Input rise and fall times ..................................... 1ns Input timing reference levels .......................... 1.5V Output reference levels ................................... 1.5V Output load ............................. See Figures 1 and 2 3.3V I/O Output Load ...

Page 21

SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time the ZZ pin is ...

Page 22

KHKH CLK EVKH KHEX KHKL CKE CVKH KHCX CE# ADV/LD# R/W# BWx ADDRESS t t AVKH KHAX DQ OE# COMMAND WRITE WRITE D(A1) D(A2) READ/WRITE TIMING PARAMETERS -6 -7.5 SYM ...

Page 23

CLK CKE# CE# ADV/LD# R/W# BWx ADDRESS DQ COMMAND WRITE READ D(A1) Q(A2) NOP, STALL, AND DESELECT TIMING PARAMETERS -6 -7.5 SYM MIN MAX MIN MAX t KHQX 1.5 1.5 t KHQZ 1.5 3.5 1.5 3.5 ...

Page 24

TYP +0.06 0.32 -0.10 PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...

Page 25

BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. DATA SHEET ...

Page 26

REVISION HISTORY Updated package drawings ................................................................................................................................... January 9/03 Removed “Preliminary Package Data” from front page .............................................................................. February 22/02 Removed 119-pin PBGA package and references ........................................................................................ February 14/02 Removed note “Not Recommended for New Designs,” Rev. 6/01 ...................................................................... June 7/01 Added ...

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