MT55L128L32P1 Micron Semiconductor Products, Inc., MT55L128L32P1 Datasheet - Page 7

• Manufacturer Part Number: MT55L128L32P1
• Description: 4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS (continued)
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
(b)
28–30, 51–53,
56, 57, 75, 78,
14, 15, 16, 41, 14, 15, 16, 41,
26, 40, 55, 60, 26, 40, 55, 60,
(a)
18, 19, 22–24
38, 39, 42, 43
54, 61, 70, 77
67, 71, 76, 90
4, 11, 20, 27,
5, 10, 17, 21,
1-3, 6, 7, 25,
63, 68, 69,
79, 95, 96
65, 66, 91
8, 9, 12, 13,
58, 59, 62,
72–74
83, 84
x18
N/A
88
31
56–59, 62, 63
72–75, 78, 79
22–25, 28, 29
38, 39, 42, 43
54, 61, 70, 77
67, 71, 76, 90
4, 11, 20, 27,
5, 10, 17, 21,
(c)
(b)
(d)
(a)
65, 66, 91
x32/x36
12, 13
83, 84
2, 3, 6–9,
N/A
52, 53,
68, 69,
18, 19,
88
51
80
30
31
1
SYMBOL
NC/DQa
NC/DQb
NC/DQd
NC/DQc
(LBO#)
MODE
R/W#
V
DQa
D Q b
D Q d
DNU
DQc
V
N C
V
N F
DD
DD
SS
Q
Output
Supply
Supply
Supply
Input/
TYPE
Input
Input
NC/
I/O
N C
–
–
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a
new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs
occur if all byte write enables are LOW.
SRAM Data I/Os: Byte “a” is DQa pins; Byte “b” is DQb
pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input
data must meet setup and hold times around the rising
edge of CLK.
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected
to GND to minimize thermal impedance. On the x36
version, these bits are DQs.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
No Function: These are internally connected to the die
and will have the capacitance of input pins. It is
allowable to leave these pins unconnected or driven by
signals. Reserved for address expansion, pin 83 becomes
an SA at 8Mb density and pin 84 becomes an SA at
16Mb density.
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
Power Supply: See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical
Characteristics and Operating Conditions for range.
Ground: GND.
7
4Mb: 256K x 18, 128K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
PIPELINED ZBT SRAM
©2003, Micron Technology, Inc.