MT55L128L32P1 Micron Semiconductor Products, Inc., MT55L128L32P1 Datasheet - Page 19

• Manufacturer Part Number: MT55L128L32P1
• Description: 4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined,
• Manufacturer: Micron Semiconductor Products, Inc.

AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0°C ≤ T
NOTE: 1. This parameter is sampled.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
10. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
2. Measured as HIGH above V
3. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
4. This parameter is sampled.
5. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
6. Transition is measured ±200mV from steady state voltage.
7. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
9. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (V
turnaround timing.
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising
edge of CLK when ADV/LD# is LOW to remain enabled.
2.5V I/O (V
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
DD
Q = +2.5V +0.4V/-0.125V).
A
≤ +70°C; V
SYMBOL
t
t
t
t
t
t
t
t
KHQX1
t
t
t
t
t
t
t
t
t
t
KHKH
KHQV
KHQX
GHQZ
AVKH
DVKH
KHAX
KHDX
KHQZ
GLQV
GLQX
EVKH
CVKH
KHEX
KHCX
KHKL
KLKH
f
KF
IH
and LOW below V
DD
= +3.3V ±0.165V; ZBT mode)
MIN
6.0
1.7
1.7
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0
-6
MAX
166
3.5
3.5
3.5
3.5
IL
.
19
MIN
7.5
2.0
2.0
1.5
1.5
1.5
1.7
1.7
1.7
1.7
0.5
0.5
0.5
0.5
0
-7.5
4Mb: 256K x 18, 128K x 32/36
MAX
133
4.2
3.5
4.2
4.2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIPELINED ZBT SRAM
MIN
3.2
3.2
1.5
1.5
1.5
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
DD
10
0
Q = +3.3V ±0.165V) and Figure 3 for
-10
MAX
100
5.0
3.5
5.0
5.0
UNITS
©2003, Micron Technology, Inc.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
NOTES
1
1
2
6
7
7
7
7
7
7
7
7