PIC16C620 Microchip Technology, PIC16C620 Datasheet - Page 56

• Manufacturer Part Number: PIC16C620
• Description: EPROM-Based 8-Bit CMOS Microcontroller
• Manufacturer: Microchip Technology

PIC16C62X
9.5.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 9.8 for
details on SLEEP and Figure 9-18 for timing of
wake-up from SLEEP through RB0/INT interrupt.
9.5.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 9-16: INT PIN INTERRUPT TIMING
TABLE 9-8:
DS30235G-page 56
Address Name
0Bh
0Ch
8Ch
Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
INSTRUCTION FLOW
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
enabled/disabled
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
RB0/INT INTERRUPT
TMR0 INTERRUPT
INTCON
PIR1
PIE1
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
SUMMARY OF INTERRUPT REGISTERS
Q1
Bit 7
Inst (PC-1)
GIE
—
—
Inst (PC)
00h) in the TMR0 register will
1
Q2
PC
by
Q3
4
CMIF
CMIE
Bit 6
PEIE
setting/clearing
Q4
5
Q1
Bit 5
T0IE
—
—
Inst (PC+1)
Inst (PC)
Q2
1
PC+1
Q3
INTE
Bit 4
—
—
T0IE
Preliminary
Q4
RBIE
Bit 3
Interrupt Latency
Q1
—
—
Dummy Cycle
Q2
9.5.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
9.5.4
See Section 7.6 for complete description of comparator
interrupts.
PC+1
—
Note:
Bit 2
T0IF
—
—
Q3
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q4
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Bit 1
INTF
—
—
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
RBIF
Bit 0
—
—
Q3
1998 Microchip Technology Inc.
Value on POR
Q4
0000 000x
-0-- ----
-0-- ----
Reset
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
other resets
Value on all
0000 000u
-0-- ----
-0-- ----
Q3
Q4
(1)