MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 33

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
Fs bits are checked (FSI set high). If the D4
secondary yellow alarm is enabled (control bit 1 -
D4SECY of Transmit Alarm Control Word page 1H,
address 11H) then the Fs bit of frame 12 is not
verified for the loss of frame circuit.
In E1 or T1 mode, receive transparent mode
(selected when bit 3 page 1 address 12H is high) no
reframing is forced by the device.
The user may initiate a software reframe at any time
by setting bit 1, page 1, address 10H high (ReFR).
Once the circuit has commenced reframing the
signalling
synchronization has been achieved.
MT9074 Channel Signaling
Channel Signaling in T1 mode
In T1 mode,when control bit RBEn (page 1H,
address 14H) is low the MT9074 will insert ABCD or
AB signaling bits into bit 8 of every transmit DS0
channel every 6th frame. The AB or ABCD signaling
bits from received frames 6 and 12 (AB) or from
frames 6, 12, 18 and 24 (ABCD) will be loaded into
an internal storage ram. The transmit AB/ ABCD
signaling nibbles can be passed either via the micro-
ports (for channels with bit 1 set high in the Per Time
Slot Control Word - pages 7H and 8H) or through
related channels of the CSTi serial links, see “Table
6 - STBUS vs. DS1 to Channel Relationship(T1)” on
page 14. The receive signaling bits are always
mapped to the equivalent ST-BUS channels on
CSTo. Memory pages five and six contain the
transmit AB or ABCD nibbles and pages eight and
nine the receive AB or ABCD nibbles for micro-port
CAS access.
The serial control streams that contain the transmit /
receive signaling information (CSTi and CSTo
respectively) are clocked at 2.048 Mhz. The number
of signaling bits to be transmit / received = 24
(timeslots) x 4 bits per timeslot (ABCD) = 24 nibbles.
This leaves many unused nibble positions in the
2.048 Mhz CSTi / CSTo bandwidth. These unused
nibble locations are tristated. The usage of the bit
stream is as follows: the signaling bits are inserted /
reported in the same CSTi / CSTo channels that
correspond to the DS1 channels used in DSTi / DSTo
- see Table , “Table 6 - STBUS vs. DS1 to Channel
Relationship(T1),” on page 14. The control bit MSN
(Signalling Control Word, page 01H, address 14H)
allows for the ABCD bit to use the most significant
nibble of CSTi / CSTo (MSN set high) or the least
significant nibble (MSN set low). Unused nibbles and
timeslots
are
bits
tristate.
are
frozen
In
order
until
to
multiframe
facilitate
multiplexing on the CSTo control stream, an
additional control bit CSToEn (Signalling Control
Word, page 01H, address 14H) will tristate the whole
stream when set low. This control bit is forced low
with the reset pin. In the case of D4 trunks, only AB
bits are reported. The control bits SM1-0 allow the
user to program the 2 unused bits reported on CSTo
in the signalling nibble otherwise occupied by CD
signalling bits in ESF trunks.
A receive signaling bit debounce of 6 msec. can be
selected (DBEn set high - Signalling Control Word,
page 01H, address 14H). It should be noted that
there may be as much as 3 msec. added to this
duration because signaling equipment state changes
are not synchronous with the D4 or ESF multiframe.
If multi - frame synchronization is lost (page 3H,
address 10H, bit 6 MFSYNC = 1) all receive
signalling bits are frozen. They will become unfrozen
when multi - frame synchronization is acquired (this
is the same as terminal frame synchronization for
ESF links).
When the SIGI interrupt is unmasked, IRQ will
become active when a signalling state change is
detected in any of the 24 receive channels. The SIGI
interrupt mask is located on page 1, address 1EH, bit
0 (set high to enable interrupt); and the SIGI interrupt
vector (page 4, address 12H) is 01H.
Channel Signaling in E1 mode
In E1 mode,when control bit TxCCS is set to one, the
MT9074 is in Common Channel Signalling (CCS)
mode. When TxCCS is low it is in Channel
Associated Signalling mode (CAS). The CAS mode
ABCD signalling nibbles can be passed either via the
micro-ports (when RPSIG = 1) or through related
channels of the CSTo and CSTi serial links (when
RPSIG = 0). Memory page 09H and 0AH contains
the receive ABCD nibbles and page 05H and 06H
the transmit ABCD nibbles for micro-port CAS
access.
In CAS operation an ABCD signalling bit debounce
of 14 msec. can be selected by writing a one to
DBNCE control bit. This is consistent with the
signalling recognition time of ITU-T Q.422. It should
be noted that there may be as much as 2 msec.
added to this duration because signalling equipment
state changes are not synchronous with the PCM 30
multiframe.
If multiframe synchronization is lost (page 03H,
address 10H, when MFSYNC = 1) all receive CAS
signalling nibbles are frozen. Receive CAS nibbles
MT9074
33