MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 47

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

Advance Information
7-0
Bit
Bit
7
6
5
4
3
2
Table 29 - Transmit Message Word (T1)
TxM7-0 Transmit Message Bits 7 - 0. The
Name
Table 30 - Error Insertion Word (T1)
CRCE
Name
PERR
BPVE
LOSE
FTE
FSE
(Page 1, Address 18H)
contents
transmitted into those outgoing DS1
channels selected by the Per Time
Slot Control registers.
(Page 1, Address 19H)
Bipolar
Insertion. A zero-to-one transition
of this bit inserts a single bipolar
violation error into the transmit
DS1 data. A one, zero or one-to-
zero transition has no function.
CRC-6 Error Insertion. A zero-to-
one transition of this bit inserts a
single
transmit ESF DS1 data. A one,
zero or one-to-zero transition has
no function.
Terminal
Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit D4 Ft pattern or the
transmit ESF framing bit pattern
(in ESF mode). A one, zero or
one-to-zero
function.
Signal
Insertion. A zero-to-one transition
of this bit inserts a single error into
the transmit Fs bits (in D4 mode
only). A one, zero or one-to-zero
transition has no function.
Loss of Signal Error Insertion. If
one, the MT9074 transmits an all
zeros signal (no pulses). Zero
code suppression is overridden. If
zero, data is transmitted normally.
Payload Error Insertion. A zero -
to - one transition of this bit inserts
a single bit error in the transmit
payload. A one, zero or one-to-
zero transition has no function.
Functional Description
Functional Description
CRC-6
of
Framing
Framing
Violation
transition
this
error
register
Bit
Bit
into
has
Error
Error
Error
the
are
no
Bit
Bit
1
0
7
6
5
4
3
Table 30 - Error Insertion Word (T1)
CNTCLR
SAMPLE
Table 31 - Reset Control Word (T1)
Name
LOS/
SPND
Name
LOF
INTA
- - -
RST
(Page 1, Address 1AH)
(Page 1, Address 19H)
Unused.
Loss of Signal or Loss of Frame
Selection. If one, pin LOS will go
high when a loss of signal state
exists (criteria as per LLOS status
bit). If low, pin LOS will go high
when either a loss of signal or a
loss of frame alignment state exits.
Software reset. Setting this bit is
equivalent
hardware reset. All counters are
cleared and the control registers
are set to their default values.
This control bit is internally
cleared after the reset operation
is complete.
Suspend Interrupts. If one, the
IRQ output will be in a high-
impedance
interrupts will be ignored. If zero,
the IRQ output will function
normally.
Interrupt Acknowledge. Setting
this bit clears all the interrupt
status bits and forces the IRQ pin
into high impedance. The control
bit itself is then internally cleared.
Counter Clear. If one, all status
error counters are cleared and
held low.
One Second Sample. Setting
this bit causes the error counters
(change of frame alignment, loss
of frame alignment, bpv errors,
crc errors, severely errored frame
events and multiframes out of
sync) to be updated on one
second intervals coincident with
the one second timer (status
page 3 address 12H bit 7).
Functional Description
Functional Description
to
state
performing
MT9074
and
all
a
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