MT90883 Zarlink Semiconductor, MT90883 Datasheet
MT90883
Related parts for MT90883
MT90883 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. MT90880B/IG/BP1N MT90881A/IG/BP1N MT90882B/IG/BP1N MT90883A/IG/BP1N Applications • Packet backplane interconnection • Circuit Emulation over packet domain • ...
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... MT908801024 bi-directional channels, integral TDM switch • MT908811024 bi-directional channels, no TDM switch • MT90882256 bi-directional channels, integral TDM switch • MT90883256 bi-directional channels, no TDM switch Feature No. of WAN streams Local Port No. of Available Channels TDM Switch Availability Master mode only ...
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... PCI SIG RMII consortium IEEE ATM Forum ATM Forum Mitel ECTF GO-MVIP Telcordia ITU-T ITU-T Table 3 - Referenced Documents 3 Zarlink Semiconductor Inc. Data Sheet Document Issue / Date Number IEEE 802.3u 1995 2.2 Rev 1.2, March 1998 IEEE 1149.1 1990 af-vtoa-0078 Ver 2.0, Jan. 1997 af-vtoa-0085 ...
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... Context Modification (Addition or deletion of physical channels 5.5.4 Context Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.5.5 Context Cleardown 6.0 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 WAN Interface and Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.1 Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1.2 Operational Modes 6.2 TDM Cross-Connect Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2.1 Multiplexing and Blocking 6.2.2 Re-ordering Timeslots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.3 Channel Broadcast 6.3 WAN Receive and Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MT90880/1/2/3 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Special Note to Users: MT9088x handling of received corrupted Ethernet packets and dealing with the next valid packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.1 Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.0.1 Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.0.2 Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.1 WAN Access Interface 10.1.1 Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.1.2 Clock Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.2 Local TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 MT90880/1/2/3 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Packet Interface 10.3.1 MII Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.2 MII Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.3 RMII Interface 10.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.5 System Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.6 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MT90880/1/2/3 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 42 - WAN Bus Clock Master Mode at 2.048 Mbs - Generic E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 43 - WAN Bus Clock Master Mode Timing at 8.192 Mbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 44 - Local Bus Timing at 2.048 Mbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 45 - Local Bus Timing at 4.096 Mbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 46 - Local Bus Timing at 8.192 Mbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 48 - MII Port Receive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MT90880/1/2/3 List of Figures 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 49 - External RAM Single Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 50 - External RAM Multi Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 51 - External RAM Single Cycle Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 52 - External RAM Multi Cycle Write Figure 53 - JTAG Clock and Reset Timing MT90880/1/2/3 List of Figures 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 33 - Local TDM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 34 - Packet Interface Timing - MII Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 35 - Packet Interface Timing - MII Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 36 - Packet Interface Timing - RMII Interface Table 37 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 38 - System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 39 - JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MT90880/1/2/3 List of Tables 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Change Signals pci_req#, pci_serr# and pci_inta# changed from open drain to normal I/O. Addition of Section 6.10.6, “Open Drain Circuitry“ showing external open drain buffer for signals pci_serr# and pci_inta#. Change DC Electrical Characterisitics were changed due to incorrect units listed. 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Ball Matrix (partially populated with GND matrix in the centre) • Ball Diameter 0.63 mm • Total Package Thickness 2.03 mm Package is viewed from the top side (e.g,. through top of the package). Note ball A1 is non-chamfered corner. MT90880/1/2/3 Figure 2 - Package View and Ball Positions 11 Zarlink Semiconductor Inc. Data Sheet ...
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... WAN_CLKI[31:24 U22 [31], V26 [30], N23 [29], P24 [28], M22 [27], N24 [26], K23 [25], L24 [24] MT90880/1/2/3 Package Balls Table 4 - WAN Access Interface 12 Zarlink Semiconductor Inc. Data Sheet Description WAN Interface serial output streams Operate at 2.048 Mbs All variants WAN Interface serial output streams Operate at 2.048 Mbs MT90880 and MT90881 variants only ...
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... MT90880 and MT90882 variants only Local TDM interface serial output streams Operate at 2.048 Mbs MT90880 variant only Local TDM interface serial output streams Operate at 2.048 and 4.096 Mbs MT90880 variant only Table 5 - Local TDM Interface 13 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... All variants Package Balls MII management data clock. Common for both MII ports. MII management data I/O Common for both MII ports; 2.5 MHz MII management interrupt for port A Transmit data Transmit enable Table 6 - MII Interfaces 14 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Collision detect MII management interrupt for port B Transmit data Transmit enable Transmit clock Receive data Receive data valid Receive clock Receive error Carrier sense Collision detect Table 6 - MII Interfaces (continued) 15 Zarlink Semiconductor Inc. Data Sheet Description (RMII specification intended for ...
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... Carrier sense & receive data valid Transmit enable Transmit data Table 7 - RMII Interface Package Balls PCI clock PCI reset PCI request PCI grant PCI address / data PCI control / byte enable PCI parity PCI frame 16 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... O U AB1 [3], AA4 [2], AB2 [1], AC1 [0] MT90880/1/2/3 Package Balls Table 8 - PCI Interface Package Balls Table 9 - External Memory Interface 17 Zarlink Semiconductor Inc. Data Sheet Description PCI target ready PCI initiator ready PCI stop PCI device select PCI ID select PCI parity error PCI system error (NOT open drain. ...
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... JTAG test clock JTAG test mode select JTAG test data input JTAG test data output Table 11 - JTAG Interface Width 18 Zarlink Semiconductor Inc. Data Sheet Description Description Description Test – Set Mode upon Reset 00 - PLL test mode 01 - Scan test mode ...
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... See Table 21. Leave unconnected in normal operation. Leave unconnected in normal operation. Leave unconnected in normal operation. Table 13 - Bootstrap Pin Functions 19 Zarlink Semiconductor Inc. Data Sheet Description IDDQ test enable. Set low for normal operation. Analog test output for system clock PLL. Leave unconnected in normal operation ...
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... This type of structure can be used in applications as diverse as telephone switches, multi-service access platforms and voice over IP gateways. Figure 2 shows a multi-service access platform based on an Ethernet backplane using the MT90880. MT90880/1/2/3 Package Balls 20 Zarlink Semiconductor Inc. Data Sheet Description 3.3 V VDD power supply 1.8 V VDD power supply 0 V power supply 1 ...
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... MT90880 TDM-IP Processor MVTX2604 Ethernet Switch MT90880 TDM-IP Processor MT90880 TDM-IP Processor IP Router Packet 21 Zarlink Semiconductor Inc. Data Sheet Remote Resource Pool MT90880 DSP TDM-IP modem Processor pool Remote Resource Pool MT90880 DSP TDM-IP codecs/ Processor echo can. Remote Resource Pool ...
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... Line Input Card Voice Traffic MT90880 MT9076 T1/E1/ TDM-IP ISDN Framer TDM Processor Modem Traffic Ethernet MVTX2604 Ethernet Switch 22 Zarlink Semiconductor Inc. Data Sheet T1/E1/ MT90880 ISDN MT9076 TDM-IP Framer/LIU Processor Circuit Emulation Interworking Function Class 5 Voice Switch TDM Packet ...
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... MT90880/1/2/3 Line Input Card MT90880 MT9076 TDM-IP Framer TDM Processor Modulated Ethernet Traffic MVTX2604 Ethernet Switch Line Input Card Remote MT90880 TDM MT9076 Modem TDM-IP Framer DSP Pool PCI Processor 23 Zarlink Semiconductor Inc. Data Sheet Packet Ethernet Demodulated packet data IP Router ...
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... PSTN T1/E1/ ISDN MT90880/1/2/3 Line Input Card Examples: HDLC, Local modem pool, Resource voice codecs, Pool echo cancellers TDM MT90880 MT9076 TDM-IP Framer TDM Processor Figure 6 - Use of a Local Resource Pool 24 Zarlink Semiconductor Inc. Data Sheet PCI Packet Ethernet ...
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... As in Figure 7, the MT90866 TDM switch is used to concentrate the TDM backplane onto the MT9088x TDM interface. This allows any channel on a bus segment to be switched onto any channel on any other bus segment. MT90880/1/2/3 MT90880 Ethernet TDM-IP Processor transparent data flow 25 Zarlink Semiconductor Inc. Data Sheet Extension H.100/H.110 bus segment MT90866 H.110 Switch ...
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... Switch this high frequency clock must be distributed around the system while maintaining accurate phase alignment the TDM backplane to a single rack, limiting the size of the system that can be connected 26 Zarlink Semiconductor Inc. Data Sheet H.100/H.110 bus segment MT90866 MT90880 H.110 ...
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... Low latency connection, with end to end delay of less than 0.5 ms, depending on user configuration MT90880/1/2/3 Transparent data flow between TDM equipment MT9088x MT9088x TDM-Packet TDM-Packet conversion conversion packet network interworking interworking function function Figure 9 - MT9088x Family Operation 27 Zarlink Semiconductor Inc. Data Sheet TDM equipment constant bit rate TDM link ...
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... PCI Interface Control WAN Packet Receive Transmit Queue Manager WAN Packet Transmit Receive Memory Manager and SSRAM Interface Controller Packet Memory 0.125 - 8 MBytes SSRAM (Burst or ZBT type) 28 Zarlink Semiconductor Inc. Data Sheet Admin. Dual Packet Interface MAC JTAG Test Controller JTAG Interface ...
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... Context modification (e.g., addition or deletion of timeslots) must also be set up in advance before the actual modification takes place. Changes are signalled out of band by the transmit end, which waits for confirmation from the receive end. This indicates that the amendments have been made, and it is ready to handle modified MT90880/1/2/3 29 Zarlink Semiconductor Inc. Data Sheet ...
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... On transmission the packet is retrieved from memory by the Packet Formatter, a pre-defined header added, and then passed to the MAC for transmission. Figure 11 - WAN to Packet Data and Control Flow MT90880/1/2/3 Local TDM Interface Host Interface Packet Memory 30 Zarlink Semiconductor Inc. Data Sheet Data Flow Control Flow ...
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... The WAN Transmit block retrieves the data from packet memory, and directs it towards the appropriate timeslots on the WAN interface. MT90880/1/2/3 Local TDM Interface Host Interface Packet Memory Figure 12 - Packet to WAN Data Flow 31 Zarlink Semiconductor Inc. Data Sheet Data Flow Control Flow ...
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... If the destination is the PCI interface, the DMA controller is used to write the packets directly into system memory. After local processing, the data is re-directed to the WAN interface by going through the Local TDM interface and the TDM switch. MT90880/1/2/3 Local Resource Pool e.g. DSP pool Packet Memory 32 Zarlink Semiconductor Inc. Data Sheet Data Flow Control Flow ...
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... On transmission the packet is retrieved from memory by the Packet Formatter in the normal way, and passed to the MAC for transmission. MT90880/1/2/3 Local Resource Pool e.g. DSP pool Packet Memory Host Processor Packet Memory Figure 15 - PCI to Packet Data Flow 33 Zarlink Semiconductor Inc. Data Sheet Data Flow Control Flow Data Flow Control Flow ...
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... Interface. A fixed order of streams and channels is maintained (see Figure 17), with channel 0, stream 0 placed before channel 0, stream 1, which is placed before channel 1, stream this order that allows the packet to be correctly disassembled at the far end. MT90880/1/2/3 Host Processor Packet Memory Figure 16 - Packet to PCI Data Flow 34 Zarlink Semiconductor Inc. Data Sheet Data Flow Control Flow ...
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... In applications where large payloads are being used, the payload size must be chosen such that the overall packet size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). MT90880/1/2/3 Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2 35 Zarlink Semiconductor Inc. Data Sheet Channel 31 Channel 31 Channel 31 Channel 31 ...
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... MT90880/1/2/3 Ethernet Header Upper Layers (optional) Context Descriptor Static Padding (if required) Channel 1 Channel 2 Channel x Channel 1 Channel 2 Channel x Channel 1 Channel 2 Channel x Ethernet FCS Ver. C Context Figure 19 - Context Descriptor Field 36 Zarlink Semiconductor Inc. Data Sheet Ethernet Payload 46 to 1500 bytes 0 ...
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... MT9088x waits for a predetermined number of TDM frames to allow for delay variation in the LAN, then automatically activates new context. The value of the context switch bit is recorded for reference. Table 15 - New Context Establishment 37 Zarlink Semiconductor Inc. Data Sheet Packet Receive End (PRX) ...
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... First packet received for the modified context, identified by the toggling of the context switch bit. This automatically activates the previously programmed context modifications. The new value of the context switch bit is recorded for reference. Table 16 - Context Modification Process 38 Zarlink Semiconductor Inc. Data Sheet Packet Receive End (PRX) ...
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... This automatically activates the previously programmed context teardown. The PRX Queue manager discards any future packets that arrive with the same context ID. Table 17 - Context Teardown Process 39 Zarlink Semiconductor Inc. Data Sheet Packet Receive End (PRX) ...
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... Clock Nominal Frequenc Frame Pulse y Width 32 2.048 MHz 488 ns 32 4.096 MHz 244 ns 16.384 61 ns 128 MHz 40 Zarlink Semiconductor Inc. Data Sheet Frame Boundary Frame Alignment Pulse frame Polarity clock pulse Per port Per port Starts at control control boundary Per port ...
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... WAN_FRMI[x]. One of these is selected as a reference for the internal DPLL, which generates the 4.096 MHz clock and the frame pulse required for the ST-bus operation. This is used both to clock data in and out of both the framer and the MT90880. The clki[31:0] inputs should be left unconnected, as shown in the figure below. MT90880/1/2/3 41 Zarlink Semiconductor Inc. Data Sheet ...
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... TDM-IP Processor WAN_STO0 WAN_CLKI0 8 KHz WAN_FRMI0 WAN_STI1 WAN_STO1 WAN_CLKI1 8 KHz WAN_FRMI1 WAN_STI31 WAN_STO31 WAN_CLKI31 8 KHz WAN_FRMI31 Master Clock Output ST-Bus 2.048Mbit/s mode 4.096 MHz WAN_CLKO 8 KHz WAN_FRMO 42 Zarlink Semiconductor Inc. Data Sheet MT90880 internally used TDM clock and frame MUX DPLL ...
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... STi7 WAN_STI7 STo7 WAN_STO7 16.384 MHz ST_CKo0 WAN_CLKI0 ST_FPo0 WAN_FRMI0 ST_CKo1 WAN_CLKI1 ST_FPo1 WAN_FRMI1 WAN_CLKI2 WAN_FRMI2 WAN_CLKI31 WAN_FRMI31 WAN_CLKO WAN_FRMO 43 Zarlink Semiconductor Inc. Data Sheet MT90880 TDM-IP Processor internal TDM clock and frame MUX DPLL Slave Mode Bypass ST-bus 8.192Mbit/s mode ...
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... Figure 22 - Connecting Framers to the MT90880 in Asynchronous Mode MT90880/1/2/3 WAN_STI0 TDM-IP Processor WAN_STO0 4.096 MHz WAN_CLKI0 8 KHz WAN_FRMI0 WAN_STI1 WAN_STO1 4.096 MHz WAN_CLKI1 8 KHz WAN_FRMI1 WAN_STI31 WAN_STO31 4.096 MHz WAN_CLKI31 8 KHz WAN_FRMI31 MUX WAN_CLKO DPLL Bypassed in Async. mode WAN_FRMO 44 Zarlink Semiconductor Inc. Data Sheet MT90880 ...
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... Rate conversion between WAN and local streams • Per-stream bit delay for the local input streams • Per-stream bit advancement for the local output streams • Per-channel constant throughput delay MT90880/1/2/3 MT9088x switch WAN Receive WAN Transmit 45 Zarlink Semiconductor Inc. Data Sheet To Packet Interface ...
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... Local interface. prevents the direct connection of WAN Access Interface stream 1, channel 0 to WAN Receive block. prevents any connection from the Local interface to stream 1, channel 0 on the WAN Access Interface. 46 Zarlink Semiconductor Inc. Data Sheet ...
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... Maintains timeslot order and TDM frame within each context. • Supports circuit emulation of structured services. • Programmable number of TDM frames per packet. • Supports payload sizes from 1 to 1500 bytes. • Allows a user-defined static header to be attached to each packet. MT90880/1/2/3 47 Zarlink Semiconductor Inc. Data Sheet ...
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... The fields within the context lookup table are shown in Figure 25. MT90880/1/2/3 context data cache memory cache buffer context control state cache address 48 Zarlink Semiconductor Inc. Data Sheet Context control state machine to external to memory packet memory manager ...
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... Transmit Controller, and that it is necessary to observe the correct sequence order to avoid mis-operation (see Table 16 on page 38). The application should ensure that following the lookup table modifications, the receiving MT90880/1/2 Figure 25 - Context Look-Up Table 49 Zarlink Semiconductor Inc. Data Sheet Context ...
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... However, the buffer can grow or shrink with time. When the variation in packet delay through the network is greater than the programmed buffer latency, occasional packets will arrive too late, and the TDM interface will be starved of data. MT90880/1/2/3 50 Zarlink Semiconductor Inc. Data Sheet ...
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... The jitter buffer will "overrun", i.e., fill up completely under the following circumstances: • If the TDM data is played out of the TDM interfaces slower than the original TDM interface • If the packet delay variation in the network is larger than the programmed jitter buffer MT90880/1/2/3 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Classes of Service The MT9088X uses two methods of queue control to provide for different classes of service: Strict Priority (SP), and Weighted Fair Queuing (WFQ). The queue disciplines can be allocated flexibly across the four different queues, as shown in Table 7. MT90880/1/2/3 52 Zarlink Semiconductor Inc. Data Sheet ...
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... The bandwidth allocation is only used to guarantee a minimum allocation to a particular traffic class, should it be required. MT90880/1/2/3 Class of Service Class 2 Class WFQ WFQ WFQ WFQ WFQ Weight % Bandwidth allocated 32 50.0 Mbs 24 37.5 Mbs 06 9.4 Mbs 02 3.1 Mbs 64 100 Mbs 53 Zarlink Semiconductor Inc. Data Sheet Class 0 WFQ WFQ WFQ WFQ ...
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... WAN Access Interface or the Local TDM interface. No priority is associated with these queues, since each WAN context is independent, and does not compete for resource against the other contexts. MT90880/1/2/3 54 Zarlink Semiconductor Inc. Data Sheet ...
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... It is also possible to use a VLAN tag to switch the packets to the correct destination in the network. Again, an Ethertype needs to be allocated to CDP to enable the traffic type to be determined in the packet classifi- cation process. • Ethernet - IPv4 - CDP MT90880/1/2/3 55 Zarlink Semiconductor Inc. Data Sheet ...
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... Generates preamble, start-of-frame delimiter and frame check sequence • Collision avoidance and contention resolution in half-duplex mode • Verifies frame check sequence and frame length, discarding frames that contain errors • Statistics collection for common MIB support: MT90880/1/2/3 56 Zarlink Semiconductor Inc. Data Sheet ...
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... Next the masked header is compared against up to four possible patterns. Again, the comparison function is across the first 64 bytes of the packet. This depth of search allows fields from layer three and four headers to be included in the classification (e.g. IP and UDP headers). MT90880/1/2/3 57 Zarlink Semiconductor Inc. Data Sheet ...
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... Priority Encoder Pattern Match Result Succesful Match Y Traffic Class TDM traffic Look-up Context Descriptor Figure 26 - Packet Classification Process 58 Zarlink Semiconductor Inc. Data Sheet FCS Mask 3 Mask 4 Masked Header Pattern 3 Pattern 4 Comparator Comparison result 4 Forward to N CPU queue 0 CPU Traffic ...
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... MAC address must be matched, Must be 0x8100 Must be set to the appropriate value for TDM traffic. Must be set to the appropriate type for TDM traffic. Will require allocation of an Ethertype by the IEEE. Must be 0b000 Must be 0b00000 59 Zarlink Semiconductor Inc. Data Sheet ...
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... Check the packet has the right IP address for TDM data. Must be set to the appropriate value for TDM traffic. Must be set to the appropriate value for TDM traffic. 60 Zarlink Semiconductor Inc. Data Sheet Comment TDM traffic Not CPU traffic 18 bytes in header before the CD ...
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... Mask If the MAC is programmed into promiscuous mode then the destination MAC address must be matched, 0x0800 (IP) 0b0100 0d20 61 Zarlink Semiconductor Inc. Data Sheet Match / Comment Comment TDM traffic Not CPU traffic 42 bytes in header before the CD Match / Comment ...
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... Don't care Mask Match / Comment If the MAC is programmed into promiscuous mode then the destination MAC address must be matched, 0x0800 (IP) 0b0100 0d20 62 Zarlink Semiconductor Inc. Data Sheet Match / Comment Comment Send packets to the CPU. Send to queue 2. Not TDM traffic ...
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... Supports a total of between 0.125 and 8 Mbytes of memory MT90880/1/2/3 Mask Match / Comment 0d6 (TCP) Check the packet has the right IP address for CPU control traffic. Value set to 0b1 set to 0b11 Don't care 63 Zarlink Semiconductor Inc. Data Sheet Comment Send packets to the CPU. Send to queue 3. Not TDM traffic ...
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... Figure 27. All four memory capacities shown in this graph can be implemented using one device (either Mbs). However, for more MT90880/1/2/3 96 128 256 512 1024 64 Zarlink Semiconductor Inc. Data Sheet 2 MByte memory 1 MByte memory 512 KByte memory 256 KByte memory TM ® 's "ZBT ...
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... SRAM. The clock to the memory is the 66 66 MHz Micron TM generic SRAM System Clock e.g. MT58L256L32P (256K x 32 bits Syncburst CLK SA SA1 SA0 ADSC# GW# OE# DQa DQb DQc DQd 65 Zarlink Semiconductor Inc. Data Sheet ADSP# BWE# CE2 CE# CE2# BWa# BWb# BWc# BWd# ADV# MODE ...
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... SSRAM size 16 Mbs 8 Mbs 4 Mbs 2 Mbs 1 Mbs Table 29 - Total Available Memory Size, Using Four External SSRAM Devices MT90880/1/2/3 Total available capacity using 4 devices 8 Mbytes 4 Mbytes 2 Mbytes 1 Mbytes 0.5 Mbytes 66 Zarlink Semiconductor Inc. Data Sheet Active address signals 20:2 19:2 18:2 17:2 16:2 ...
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... DQa DQb DQa DQb DQc DQb DQc DQb DQd DQc DQd DQc DQd DQd = S_CLK RDV DS is 1.5 ns when using the 7.5 ns speed DS 67 Zarlink Semiconductor Inc. Data Sheet TM ) generic SRAM GW# ADSP# CE2 GW# ADSP# CE2 BWE# CE# CE2 CE2# CE# BWa# CE2# ...
Page 68
... S_CLK. In response, the RAM puts the data out onto the bus within a to S_CLK back at the MT90880. Since both RDS is determined by the equation: OEQ - S_CLK RAV RDS = 15. 4.65 ns OEQ 68 Zarlink Semiconductor Inc. Data Sheet is 4.2 ns. This part therefore meets the ...
Page 69
... The MT9088x is configured as a PCI Satellite device. Therefore the PCI interface must be configured by the Host PCI device connected to the bus before the internal register and memory space can be accessed by the Host. This is achieved by programming the device PCI configuration registers. MT90880/1/2/3 69 Zarlink Semiconductor Inc. Data Sheet ...
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... The 5 V PCI signalling environment is not supported as the MT9088x PCI Interface is not 5 V tolerant. MT90880/1/2/3 Memory Base Address Allocated to MT90880 by system software (up to 8MB of 16MB used) External Packet Memory space of MT90880 70 Zarlink Semiconductor Inc. Data Sheet 0xFFFFFFFF ...
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... CPU into the packet network, and to direct packets received from the network to the CPU. Figure 32 - DMA Transfer to/from System Memory MT90880/1/2/3 VDD33 (AB24) Quad Open Drain Buffer (AF19) Host CPU System memory PCI Bridge DMA transfer PCI Bus External packet MT90880 memory 71 Zarlink Semiconductor Inc. Data Sheet to PCI Backplane (3.3V) ...
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... DMA to point to the next set of descriptors. MT90880/1/2/3 Link Link Command Command Buffer Pointer Buffer Pointer Status Status Data Buffer Data Buffer Figure 33 - Descriptor Ring Structure 72 Zarlink Semiconductor Inc. Data Sheet Link Command Buffer Pointer Status Data Buffer ...
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... TDM domain. Unmatched traffic is always sent to CPU queue 0. MT90880/1/2/3 Link Link Command Command Buffer Pointer Buffer Pointer Status Status Data Buffer Data Buffer Figure 34 - Descriptor List Structure 73 Zarlink Semiconductor Inc. Data Sheet Link End Command Buffer Pointer Status Data Buffer ...
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... Test" (BST). An external Test Access Port (TAP) Controller controls the operation of the boundary scan circuitry. Details of the contents of the scan register are contained in the BSDL file. MT90880/1/2/3 CPU queues Ring/List 0 L2P queue 0 Ring/List 1 L2P queue 1 Ring/List 2 L2P queue 2 Ring/List 3 L2P queue 3 74 Zarlink Semiconductor Inc. Data Sheet Descriptor lists in System Memory ...
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... The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. Device Identification Register The device identification register is a 32-bit register. The register contents are included in the BSDL file for the chip. MT90880/1/2/3 75 Zarlink Semiconductor Inc. Data Sheet when it is not driven from ...
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... In Holdover, the DPLL maintains the clock frequency at the value recorded before the reference was judged to have failed. Holdover is typically used for short durations while network synchronization is temporarily disrupted. The initial accuracy of the held frequency is ± 0.06 ppm, which translates in the worst case to 42 frame (125 µ s) slips in 24 hours. MT90880/1/2/3 76 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 36 around 0dB of the jitter transfer amplitude. From this diagram it is possible to see that the DPLL is a second order, type 2 PLL. Figure 36 - DPLL Jitter Transfer Function Diagram Across a Wide Range of Frequencies MT90880/1/2 So change in temperature may result in an additional frequency 77 Zarlink Semiconductor Inc. Data Sheet ...
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... The DPLL outputs have a frequency accuracy of ± 0.005 ppm plus the accuracy of the master clock. For example, clock output C8OB will have a frequency of 8.192 MHz ± S_CLK accuracy ± 0.005 ppm). MT90880/1/2/3 78 Zarlink Semiconductor Inc. Data Sheet ...
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... The next valid packet following the error packet will be lost and this may belong to a different context. MT90880/1/2/3 Min Max Units ± 3.8 ± 245 50 ± 0.005 56 ± 0. Zarlink Semiconductor Inc. Data Sheet Comment ns Note 1 ppm Note 2 s ppm Note 3 ppm Note 4 ppm Note 5 ns ...
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... PLL supply voltages. MT90880/1/2/3 Voltage measurements are with respect to ground (V Symbol Min. V -0.5 DD_IO V -0.5 DD_CORE V -0.5 DD_PLL V -0 -0.5 I_5 -55 80 Zarlink Semiconductor Inc. Data Sheet ) unless otherwise stated. SS Max. Units 5.0 V 2 7.0 V ± ± ° C +125 ...
Page 81
... Max. ± LEIP I 2 LEOP - 220 DD_CORE I 1.25 DD_PLL I 100 DD_IO 81 Zarlink Semiconductor Inc. Data Sheet . ) unless otherwise stated SS Test Max. Units Condition ° C +85 ° C 125 ° C/w 3.6 V 1.95 V 1. DD_IO 5.5 V Units Test Condition µ ...
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... 1.2 T- Symbol Min. Typ. Max Zarlink Semiconductor Inc. Data Sheet Units Test Condition Units Test Condition PCI Bus mA PCI Bus mA Note 1 mA Note 1 mA Note 2 mA Note 2 ...
Page 83
... FOIH t STOD t STIS t STIH Channel 0 Bit 7 tC4L tC4L tC4H tC4H tFOIH tFOIS tSTIH tSTIS B0 B7 tSTOD Ch 0 Bit 7 83 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Notes 16.384 MHz Note 4.096 MHz Note 1 122 ns 122 ns 2.048 MHz Note 1 ...
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... Channel 0 bit 7 Channel 127 bit 0 Channel 0 bit 7 tC16H tC16H tC16L tC16L tFOIS tFOIS tSTIH tSTIH tSTIS Ch0 bit7 tSTOD tSTOD Channel 127 bit 0 Channel 0 bit 7 84 Zarlink Semiconductor Inc. Data Sheet Channel 0 bit 6 tSTOD Channel 0 bit 6 Channel 0 bit 6 tSTIH tSTIS tSTOD ...
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... C2L t FOD t STOD t STIS t STIH Channel 0 Bit 7 tC4L tC4L tC4H tC4H tFOD tFOD tSTIH tSTIS B0 B7 tSTOD Ch 0 Bit 7 85 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Notes 16.384 MHz 4.096 MHz 122 ns 122 ns 2.048 MHz 244 ns 244 ...
Page 86
... C16F t 30 C16H t 30 C16L f 8.192 C8F t 61 C8H t 61 C8L f 4.096 C4F 86 Zarlink Semiconductor Inc. Data Sheet Channel 0 Bit 6 tFOD tSTIH tSTIS tSTOD Ch 0 Bit 6 Channel 0 Bit 6 tFOD tSTIH tSTIS tSTOD Ch 0 Bit 6 Units Notes MHz ns ns MHz ns ns ...
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... Ch 0 Bit 7 Channel 0 Bit 7 tC8L tC8L tC8H tC8H tFOD tFOD tSTIH tSTIS tSTOD Ch 0 Bit 7 87 Zarlink Semiconductor Inc. Data Sheet Channel 0 Bit 6 tSTIH tSTIS tSTOD Ch 0 Bit 6 Channel 0 Bit 6 tSTIH tSTIS tSTOD Ch 0 Bit 6 ...
Page 88
... Max 400 CC t 140 - 260 CHI t 140 - 260 CLO Zarlink Semiconductor Inc. Data Sheet Channel 0 Bit 6 tSTIH tSTIS tSTOD Ch 0 Bit 6 100 Mbs Units Min. Typ. Max ...
Page 89
... DVH t 140 200 CH t 140 200 400 CC tCC tCC tDVS tDH tDS Figure 48 - MII Port Receive Characteristics 89 Zarlink Semiconductor Inc. Data Sheet tCHI tCHI tCLO tCLO tEV 100 Mbs Units Min. Typ. Max 260 14 20 ...
Page 90
... MT90880/1/2/3 Symbol Min. Typ. Max Symbol Min. Typ. Max RDV T 7.5 RAV T 3 RDS T 0 RDH Table 37 - External Memory Timing 90 Zarlink Semiconductor Inc. Data Sheet Units Notes ± 50 ppm MHz % Units Notes ...
Page 91
... Figure 49 - External RAM Single Cycle Read 1 2 S_CLK Trav RAM_A A1 Trav RAM_ADSC RAM_OE Trav RAM_RW RAM_D Figure 50 - External RAM Multi Cycle Read MT90880/1/2 Trav Trds Trav Trav Trdh Trds Zarlink Semiconductor Inc. Data Sheet 5 6 Trdh ...
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... Trdv RAM_D Figure 51 - External RAM Single Cycle Write 1 2 S_CLK Trav RAM_A Trav RAM_ADSC Trav RAM_RW RAM_OE Trdv RAM_D Figure 52 - External RAM Multi Cycle Write MT90880/1/2 Zarlink Semiconductor Inc. Data Sheet ...
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... RST t 5 JSU JDV TPSU t 15 TPH t 0 TPODV t 0 TPZ Table 39 - JTAG Interface 93 Zarlink Semiconductor Inc. Data Sheet Units Notes MHz Notes 1 and 2 ppm Note 3 ppm Note 4 Max. Units Notes 25 MHz - Note Note 2 ...
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... MT90880/1/2/3 JTAG Clock Timing t RST TRST Figure 53 - JTAG Clock and Reset Timing 94 Zarlink Semiconductor Inc Low HIGH t CYC t RSTSU Data Sheet ...
Page 95
... Standard Telecom Bus, a standard interface for TDM data streams Time Division Multiplexing TDM WAN Wide Area Network WFQ Weighted Fair Queuing WRED Weighted Random Early Discard ZBT Zero Bus Turnaround, a type of synchronous SRAM 0x Denotes Hexadecimal notation 0b Denotes binary notation MT90880/1/2/3 95 Zarlink Semiconductor Inc. Data Sheet ...
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... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...