MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 73

• Manufacturer Part Number: MT90883
• Description: (MT90880 - MT90883) TDM to Packet Processors
• Manufacturer: Zarlink Semiconductor

Full details of the DMA descriptor data structures, and the fields within the descriptor, are provided in the
"MT90880 Programmers' Model " (related document 1).
6.11.2
For data transfer from the CPU to the MT90880 (denoted "P2L", or Processor to LAN traffic), the DMA engine
transfers packets until it reaches the end of the populated data structure. An interrupt can be generated each
time a packet is transferred, or alternatively, it can be programmed to occur once the whole populated structure
has been transferred. Data transfer is resumed on CPU command once there are more packets to transfer in
system memory.
Packet and Descriptor Queues
The MT9088x family devices contain four separate queues to each port in the packet interface. These four
queues are assigned different priorities, enabling different classes of service to be defined. Fields within the
descriptor command direct the packet to the appropriate queue and port.
In addition, the device supports the use of two entirely separate descriptor structures for P2L traffic. One of
these, P2L queue 0, is given higher priority than the other, P2L queue 1. This enables high priority traffic from
the CPU to be given preferential access to the DMA. The ratio of DMA bandwidth allocated to each queue can
be adjusted from 2:1 in favour of P2L queue 0, to 8:1. Alternatively, strict priority may be used, where packets in
P2L queue 1 only get transferred if there are no packets in P2L queue 0. This is the default option.
6.11.3
For data transfer from the MT90880 to the CPU (denoted "L2P", or LAN to Processor traffic), the DMA
automatically transfers packets as they arrive from the network. The data is placed into the data buffers in
system memory until either the data structure is full or there are no more packets to transfer. When subsequent
packets arrive, data transfer is resumed automatically, provided that the structure is not full.
An interrupt may be generated each time a packet is transferred to inform the CPU that there is a packet ready
to be read, alternatively the CPU can periodically poll the descriptor status to check for new packets. The CPU
can process the incoming packet stream at any rate it chooses because the DMA will suspend the transfer
when there are no empty descriptors available.
CPU Queues
The MT90880 maintains four separate queues of packets waiting for transfer to the CPU. Each queue has a
corresponding descriptor list or ring held in System Memory (see Figure 35). Packets are classified as they are
received by the device to determine their destination. The classification process can identify up to four separate
traffic types, and each type placed into one of the four queues or directed to the TDM domain. Unmatched traffic
is always sent to CPU queue 0.
Data Transfer from CPU to MT90880
Data Transfer from MT90880 to CPU
Head Descriptor
Buffer Pointer
Data Buffer
Command
Status
Link
Figure 34 - Descriptor List Structure
Buffer Pointer
Data Buffer
Command
Status
Link
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MT90880/1/2/3
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Buffer Pointer
Data Buffer
Command
Status
Link
Buffer Pointer
Data Buffer
Command
Status
Link
End
Data Sheet