MT90883 Zarlink Semiconductor, MT90883 Datasheet - Page 67
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
MT90883
Manufacturer Part Number
MT90883
Description
(MT90880 - MT90883) TDM to Packet Processors
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90883.pdf
(97 pages)
- Current page: 67 of 97
- Download datasheet (703Kb)
6.9.4
The timings for the external memory interface are shown in Table 39. However, calculations to see whether the
MT90880 will be capable of operation with a particular memory device also depend on some external factors,
notably the skew on the board between the system clock S_CLK at the MT90880 and the memory device.
For example, the diagram in Figure 52 shows the memory write cycle. The MT90880 puts out the data on the
bus at time T
S_CLK at the RAM (T
RAM than at the MT90880, the setup time is effectively increased by the amount of skew.
The maximum clock skew between devices can be determined from the following equation:
For a Micron MT58L256L32P, the minimum RAM data setup time T
grade part. T
ns. Therefore,
Maximum allowable clock skew
External Memory Interface Timing
RDV
RDV
is 10 ns (from Table 41) and with S_CLK running at 66 MHz, the clock period T
Figure 29 - Connecting the MT90880 to Multiple External Memory Devices
following the rising edge of S_CLK. This has to meet a setup time to the next rising edge of
MT9088x device
DS
). However, if the clock is skewed on the board such that S_CLK is slightly earlier at the
RAM_D[23:16]
RAM_D[31:24]
RAM_ADSC#
RAM_WE[0]#
RAM_WE[1]#
RAM_WE[2]#
RAM_WE[3]#
RAM_D[15:8]
RAM_A[19:4]
RAM_OE[0]#
RAM_OE[1]#
RAM_OE[2]#
RAM_OE[3]#
RAM_D[7:0]
RAM_A[3]
RAM_A[2]
S_CLK
66 MHz
System Clock
= T
Zarlink Semiconductor Inc.
MT90880/1/2/3
S_CLK
- T
67
RDV
Micron
CLK
SA
SA1
SA0
ADSC#
GW#
OE#
DQa
DQb
DQc
DQd
(256K x 32 bits Syncburst
e.g. MT58L256L32P
- T
Micron
CLK
SA
SA1
SA0
ADSC#
GW#
OE#
DQa
DQb
DQc
DQd
(256K x 32 bits Syncburst
TM
DS
e.g. MT58L256L32P
generic SRAM
Micron
CLK
SA
SA1
SA0
ADSC#
GW#
OE#
DQa
DQb
DQc
DQd
(256K x 32 bits Syncburst
TM
DS
e.g. MT58L256L32P
generic SRAM
Micron
CLK
SA
SA1
SA0
ADSC#
GW#
OE#
DQa
DQb
DQc
DQd
(256K x 32 bits Syncburst
TM
is 1.5 ns when using the 7.5 ns speed
ADSP#
MODE
BWa#
BWb#
BWd#
BWc#
e.g. MT58L256L32P
ADV#
CE2#
GW#
generic SRAM
CE2
CE#
TM
ZZ
TM
)
ADSP#
MODE
BWa#
BWb#
BWc#
BWd#
ADV#
CE2#
GW#
generic SRAM
CE2
CE#
TM
ZZ
)
ADSP#
MODE
BWa#
BWb#
BWd#
BWc#
ADV#
CE2#
GW#
CE2
CE#
TM
ZZ
)
ADSP#
MODE
BWE#
BWa#
BWb#
BWd#
BWc#
ADV#
CE2#
CE2
CE#
TM
ZZ
)
V
V
DD
SS
S_CLK
Data Sheet
is 15.15
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