IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 12

• Manufacturer Part Number: IDT70T633
• Description: 512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
• Manufacturer: Integrated Device Technology

DATA
BUSY
Waveform of Read Cycles
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. t
4. Start of valid data depends on which timing becomes effective last: t
5. SEM = V
6. CE = L occurs when CE
Timing of Power-Up Power-Down
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
UB, LB
ADDR
has no relation to valid output data.
BDD
R/W
OUT
OUT
CE
OE
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
(6)
IH
.
0
= V
IL
CE
I
I
CC
and CE
SB
1
= V
t
IH
LZ
. CE = H when CE
t
t
t
/t
t
AA
ACE
AOE
ABE
LZOB
(4)
t
(4)
PU
(4)
(4)
(5)
(1)
0
50%
= V
AOE
t
RC
IH
, t
and/or CE
ACE
t
, t
BDD
12
AA
, t
(3,4)
ABE
1
= V
, or t
IL
.
BDD
t
.
VALID DATA
PD
Industrial and Commercial Temperature Ranges
50%
(4)
5670 drw 07
t
HZ
.
(2)
t
OH
5670 drw 06
.