IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 22

• Manufacturer Part Number: IDT70T633
• Description: 512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
• Manufacturer: Integrated Device Technology

Busy Logic
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T633/1 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = V
as a slave (M/S pin = V
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
A
other part of the word.
19
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Figure 3. Busy and chip enable routing for both width and depth
Busy Logic provides a hardware indication that both ports of the RAM
The use of BUSY logic is not required or desirable for all applications.
The BUSY outputs on the IDT70T633/1 RAM in master mode, are
When expanding an IDT70T633/1 RAM array in width while using
If two or more master parts were used when expanding in width, a
The BUSY arbitration on a master is based on the chip enable and
expansion with IDT70T633/1 Dual-Port RAMs.
MASTER
Dual Port RAM
BUSY
MASTER
Dual Port RAM
BUSY
L
L
IH
), and the BUSY pin is an input if the part used
IL
BUSY
BUSY
) as shown in Figure 3.
CE
CE
R
0
1
R
BUSY
SLAVE
Dual Port RAM
BUSY
SLAVE
Dual Port RAM
L
L
BUSY
BUSY
CE
CE
R
0
R
1
5670 drw 20
.
22
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
and corrupted data in the slave.
Semaphores
CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example,
the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other shared
resource.
being completely independent of each other. This means that the
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE
SEM, the semaphore enable. The CE
chip power down circuitry that permits the respective port to go into standby
mode when not selected.
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the hardware
semaphores of the IDT70T633/1, which provide a lockout mechanism
without requiring complex programming.
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T633/1 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
activity on the left port in no way slows the access time of the right port.
observe this timing can result in a glitched internal write inhibit signal
actual write pulse can be initiated with the R/W signal. Failure to
The IDT70T633/1 is an extremely fast Dual-Port 512/256K x 18
The Dual-Port RAM features a fast access time, with both ports
Systems which can best use the IDT70T633/1 contain multiple
Software handshaking between processors offers the maximum in
An advantage of using semaphores rather than the more common
The semaphore logic is a set of eight latches which are indepen-
Industrial and Commercial Temperature Ranges
0
and CE
1
, the Dual-Port RAM chip enables, and
0
, CE
1
, and SEM pins control on-