IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 14

• Manufacturer Part Number: IDT70T633
• Description: 512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
• Manufacturer: Integrated Device Technology

RapidWrite Mode Write Cycle
the IDT70T651/9 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles.
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle
NOTES:
1. OE = V
2. A write occurs during the overlap (t
3. If the CE or SEM = V
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
6. To access RAM, CE = V
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
CE or SEM
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
(Figure 1).
and CE
Unlike other vendors' Asynchronous Random Access Memories,
During this new RapidWrite Mode, the end of the write cycle is now
ADDRESS
DATA
1
IL
DATA
= V
for this timing waveform as shown. OE may equal V
IH
R/W
BEn
. CE = V
OUT
(6)
IN
IL
IH
transition occurs simultaneously with or after the R/W = V
IL
when CE
and SEM = V
EW
0
= V
or t
IH
IH
WP
. To access semaphore, CE = V
and/or CE
) of a CE = V
t
WC
t
WZ
t
EW
(5)
1
(2)
t
WP
= V
t
IL
DW
IL,
.
BEn = V
IH
with same write functionality; I/O would then always be in High-Z state.
t
DH
IL
, and a R/W = V
IH
14
and SEM = V
t
which the Address inputs must be stable. Input data setup and hold times
(t
this RapidWrite Mode the I/O will remain in the Input mode for the duration
of the operations due to R/W being held low. All standard Write Cycle
specifications must be adhered to. However, t
applicable when switching between read and write operations. Also,
there are two additional conditions on the Address Inputs that must also
be met to ensure correct address controlled writes. These specifications,
the Allowable Address Skew (t
must be met to use the RapidWrite Mode. If these conditions are not met
there is the potential for inadvertent write operations at random intermediate
locations as the device transitions between the desired write addresses.
WC
IL
DW
transition, the outputs remain in the High-impedance state.
(4)
Care must be taken to still meet the Write Cycle time (t
and t
IL
for memory array writing cycle. The last transition LOW of CE, BEn, and
IL
DH
. t
t
DW
) will now be referenced to the ending address transition. In
EW
must be met for either condition. CE = V
Industrial and Commercial Temperature Ranges
t
DH
AAS
t
WC
) and the Address Rise/Fall time (t
t
DW
t
t
WR
DH
t
OW
AS
(5)
IL
when CE
and t
5670 drw 08
WC
WR
), the time in
0
are only
= V
(1,3)
IL
ARF
),