IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 25

• Manufacturer Part Number: IDT70T633
• Description: 512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
• Manufacturer: Integrated Device Technology

JTAG AC Electrical
Characteristics
Sleep Mode
mode on both ports. The sleep mode pin on both ports is active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will have the lowest possible power
consumption. The sleep mode timing diagram demonstrates the modes of
operation: Normal Operation, No Read/Write Allowed and Sleep Mode.
JTAG Timing Specifications
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
The IDT70T633/1 is equipped with an optional sleep or low power
For a period of time prior to sleep mode and after recovering from sleep
Symbol
t
Device Outputs
t
t
JRSR
JCYC
t
t
JRST
t
t
JCH
JCL
t
t
JCD
JDC
t
t
JR
JF
JS
JH
Device Inputs
TDI/TMS
JTAG Clock Input Period
TRST
JTAG Data Output Hold
JTAG Clock Rise Time
JTAG Reset Recovery
JTAG Clock Fall Time
TDO
TCK
JTAG Clock HIGH
JTAG Data Output
JTAG Clock Low
(1)
(2)
JTAG Reset
JTAG Setup
JTAG Hold
Parameter
/
/
(1,2,3,4,5)
t
JF
t
JRST
t
JCL
t
t
Min.
JRSR
100
JR
____
____
____
40
40
50
50
15
15
0
t
JCYC
t
JS
70T633/1
Max.
____
____
____
3
3
____
____
____
____
____
25
t
(1)
(1)
t
JH
JCH
5670 tbl 20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
mode (t
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
nects its internal buffer. All outputs will remain in high-Z state while in sleep
mode. All inputs are allowed to toggle, but the RAM will not be selected and
will not perform any reads or writes.
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
5. JTAG cannot be tested in sleep mode.
any speed specified in this datasheet.
During sleep mode the RAM automatically deselects itself and discon-
ZZS
and t
ZZR
Industrial and Commercial Temperature Ranges
), new reads or writes are not allowed. If a write or read
t
JDC
t
JCD
5670 drw 23
x