HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 11

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

interrupt is enabled (by setting SBEN; bit 4 of the
SBCR), and the stack is not full and the SIF is set, a sub-
routine call to location 18H occurs.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
It is recommended that a program does not use the
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. Instead of a
crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
Rev. 1.10
External Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
USB Interrupt
A/D Converter Interrupt
Serial Interface Interrupt
CALL subroutine within the interrupt subroutine. In-
Interrupt Source
System Oscillator
Priority
1
2
3
4
5
6
Vector
0CH
04H
08H
10H
14H
18H
11
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters a power down mode and the system
clock is stopped, but the WDT oscillator still works. The
WDT oscillator can be disabled by ROM code option to
conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog timer can be disabled by
options. If the watchdog timer is disabled, all executions
related to the WDT results in no operation.
Once an internal WDT oscillator (RC oscillator with a pe-
riod of 65 s, normally at 5V) is selected, it is divided by
2
WDT time-out minimum period is 300ms~600ms. This
time-out period may vary with temperature, VDD and
process variations. By selection from the WDT option,
longer time-out periods can be realized. If the WDT
time-out is selected as 2
riod is divided by 2
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a warm reset
and only the Program Counter and SP are reset to zero.
To clear the contents of WDT, three methods are
adopted; external reset (a low level to RES), software in-
structions, or a HALT instruction. The software instruc-
tions include CLR WDT and the other set CLR
WDT1 and CLR WDT2 . Of these two types of instruc-
tion, only one can be active depending on the option
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In case
must be executed to clear the WDT, otherwise, the WDT
may reset the chip due to time-out.
CLR WDT times selection option . If the CLR WDT is
CLRWDT times equal two), these two instructions
CLR WDT1 and CLR WDT2 are chosen (i.e.
12
~2
15
(by option to get the WDT time-out period). The
15
~2
16
15
which about 2.3s~4.7s.
, the maximum time-out pe-
September 7, 2006
HT46RB50