HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 16

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

In the pulse width measurement mode with the values of
the T0ON/T1ON and T0E/T1E bits equal to 1, after the
TMR0 (TMR1) has received a transient from low to high
(or high to low if the T0E/T1E bit is 0 ), it will start count-
ing until the TMR0 (TMR1) returns to the original level
and resets the T0ON/T1ON. The measured result re-
mains in the timer/event counter even if the activated
transient occurs again. In other words, only 1-cycle
measurement can be made until the T0ON/T1ON is set.
The cycle measurement will re-function as long as it re-
ceives further transient pulse. In this operation mode,
the timer/event counter begins counting not according
to the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt re-
quest, as in the other two modes, i.e., event and timer
modes.
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of the TMR0C; T10N: bit 4 of the TMR1C)
should be set to 1. In the pulse width measurement
mode, the T0ON/T1ON is automatically cleared after
the measurement cycle is completed. But in the other
two modes, the T0ON/T1ON can only be reset by in-
structions. The overflow of the Timer/Event Counter 0/1
is one of the wake-up sources. No matter what the oper-
ation mode is, writing a 0 to ET0I or ET1I disables the re-
lated interrupt service.
Rev. 1.10
Bit No.
0
1
2
3
4
5
6
7
T0PSC0
T0PSC1
T0PSC2
Label
T0ON
T0M0
T0M1
T0E
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
Defines the TMR active edge of the timer/ event counter
(0=active on low to high; 1=active on high to low)
Enable/disable timer counting (0=disable; 1=enable)
Unused bit, read as 0
Defines the operating mode, T0M1, T0M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
INT
INT
INT
INT
INT
INT
INT
INT
=f
=f
=f
=f
=f
=f
=f
=f
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
/2
/4
/8
/16
/32
/64
/128
TMR0C (0EH) Register
16
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may re-
sults in a counting error. Blocking of the clock should be
taken into account by the programmer. It is strongly rec-
ommended to load a desired value into the TMR0/TMR1
register first, before turning on the related timer/event
counter, for proper operation since the initial value of
TMR0/TMR1 is unknown. Due to the timer/event
scheme, the programmer should pay special attention
on the instruction to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event function, to avoid unpredictable result. After
this procedure, the timer/event function can be operated
normally.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
timer prescaler is also used as the PWM counter.
Function
September 7, 2006
HT46RB50