HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 17

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Input/Output Ports
There are 38 bidirectional input/output lines in the
microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1A] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction MOV
A,[m] (m=12H, 14H, 16H, 18H or 1A). For output oper-
ation, all the data is latched and remains unchanged un-
til the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must write a 1 . The input source also
Rev. 1.10
Bit No.
0~2, 5
3
4
6
7
Label
T1ON
T1M0
T1M1
T1E
Unused bit, read as 0
Defines the TMR active edge of the timer/ event counter
(0=active on low to high; 1=active on high to low)
Enable/disable timer counting (0=disable; 1=enable)
Defines the operating mode, T1M1, T1M0:
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Input/Output Ports
17
depends on the control register. If the control register bit
is 1 the input will read the pad state. If the control reg-
ister bit is 0 the contents of the latches will move to the
internal bus. The latter is possible in the Read-modify-
write instruction. For output function, CMOS is the only
configuration. These control registers are mapped to lo-
cations 13H, 15H, 17H, 19H and 1BH.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H, 18H or 1AH ) instructions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Function
September 7, 2006
HT46RB50