HT46RB50 Holtek Semiconductor, HT46RB50 Datasheet - Page 19

• Manufacturer Part Number: HT46RB50
• Description: A/D Type USB 8-Bit MCU
• Manufacturer: Holtek Semiconductor

A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle 0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
Group 2 is denoted by AC which is the value of PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
A/D Converter
This microcontroller has 8 channels and 10-bit resolu-
tion A/D (9-bit accuracy) converter. The reference volt-
age is VDD. The A/D converter contains 4 special
registers which are; ADRL (30H), ADRH (31H), ADCR
(32H) and ACSR (33H). The ADRH and ADRL are A/D
result register higher-order byte and lower-order byte
and are read-only. After the A/D conversion is com-
pleted, the ADRH and ADRL should be read to get the
conversion result data. The ADCR is an A/D converter
control register, which defines the A/D channel number,
analog channel select, start A/D conversion control bit
and end of A/D conversion flag. If users want to start an
A/D conversion, first, define PB configuration, select the
converted analog channel, and give START bit a raising
edge and falling edge (0 1 0). At the end of A/D con-
version, the EOCB bit is cleared and an A/D converter
interrupt occurs (if the A/D converter interrupt is en-
abled). The ACSR is A/D clock setting register, which is
used to select the A/D clock source.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There s a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line determined by these 3 bits. Once a PB
line is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is powered on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
Rev. 1.10
f
f
SYS
SYS
Modulation Frequency
Modulation cycle i
/64 for (6+2) bits mode
/128 for (7+1) bits mode
Parameter
(i=0~1)
PWM
AC (0~1)
PWM Cycle
i<AC
i AC
Frequency
f
SYS
/256
Duty Cycle
PWM Cycle
[PWM]/256
DC+1
128
128
DC
Duty
19
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure that A/D conversion is completed, the
START bit should remain at 0 until the EOCB is
cleared to 0 (end of A/D conversion).
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to 1
when the START bit is set from 0 to 1 .
Important Note for A/D initialisation:
Special care must be taken to initialise the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialisation is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialis-
ation is not required.
Bit 7 of the ACSR register is used for test purposes only
Bit No. Label
Bit No. Label
2~6
0
1
7
0
1
2
3
4
5
6
7
ADCS0
ADCS1
TEST
ACS0
ACS1
ACS2
PCR0
PCR1
PCR2
EOCB
START
ADCR (32H) Register
ACSR (33H) Register
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= Undefined
Unused bit, read as 0
For test mode used only
Defines the analog channel select
Defines the Port B configuration se-
lect. If PCR0, PCR1 and PCR2 are all
zero, the ADC circuit is powered off to
reduce power consumption
Indicates end of A/D conversion.
(0= end of A/D conversion)
Each time bits 3~5 change state the
A/D should be initialised by issuing a
START signal, otherwise the EOCB
flag may have an undefined condi-
tion. See Important note for A/D in-
itialisation .
Starts the A/D conversion.
0 1 0= Start
0 1= Reset A/D converter and set
EOCB to 1 .
Function
Function
September 7, 2006
HT46RB50