DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 105

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

18.1.4 HDLC/BOC Register Description
HCRA: HDLC CONTROL REGISTER FRAMER A (Address = 00 Hex)
HCRB: HDLC CONTROL REGISTER FRAMER B (Address = A0 Hex)
(MSB)
RBR
SYMBOL
TCRCD
TEOM
TABT
TZSD
RBR
RHR
THR
TFS
RHR
POSITION
HCR.7
HCR.6
HCR.5
HCR.4
HCR.3
HCR.2
HCR.1
HCR.0
TFS
NAME AND DESCRIPTION
Receive BOC Reset. A 0 to 1 transition will reset the BOC
circuitry. Must be cleared and set again for a subsequent reset.
Receive HDLC Reset. A 0 to 1 transition will reset the
HDLC controller. Must be cleared and set again for a
subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC Reset. A 0 to 1 transition will reset both the
HDLC controller and the transmit BOC circuitry. Must be
cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
Transmit End of Message. Should be set to a 1 just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
THR
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TABT
TEOM
TZSD
TCRCD
(LSB)
DS2196