DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 118

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

19.
The line interface function in the DS2196 contains three sections; (1) the receiver which handles clock
and data recovery, (2) the transmitter which wave shapes and drives the T1 line, and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Inter-face Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER FRAMER A
(Address = 7C Hex)
19.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2196 contains a digital clock recovery system. See the DS2196 Block Diagram in Section 1 and
Figure 19–1 for more details. The DS2196 couples to the receive T1 twisted pair via a 1:1 transformer.
See Table 19–2 for transformer details. The 1.544 MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock
and data. This over sampling technique offers outstanding jitter tolerance (see Figure 19–2).
LBOS2
(MSB)
SYMBOL
LBOS2
LBOS1
LBOS0
JABDS
EGL
TPD
DJA
JAS
LINE INTERFACE FUNCTION
LBOS1
POSITION
LICR.7
LICR.6
LICR.5
LICR.4
LICR.3
LICR.2
LICR.1
LICR.0
LBOS0
NAME AND DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out; see
the Table 19–1
Line Build Out Select Bit 1. Sets the transmitter build out; see
the Table 19–1
Line Build Out Select Bit 0. Sets the transmitter build out; see
the Table 19–1
Receive Equalizer Gain Limit.
0 = –36 dB
1 = –15 dB
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
EGL
118 of 157
JAS
JABDS
DJA
(LSB)
TPD
DS2196