DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 89

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Table 15-1: BERT PATTERN SELECT OPTIONS
BC1: BERT Control Register 1 (Address = 41 Hex)
IESYNC
PS2
(MSB)
0
0
0
0
1
1
1
1
SYMBOL
IESYNC
IEBED
RPL3
RPL2
RPL1
RPL0
IEOF
–
PS1
0
0
1
1
0
0
1
1
IEBED
PS0
0
1
0
1
0
1
0
1
POSITION
BC1.7
BC1.6
BC1.5
BC1.4
BC1.3
BC1.2
BC1.1
BC1.0
Pseudorandom 2E7 – 1
Pseudorandom 2E11 – 1
Pseudorandom 2E15 – 1
Pseudorandom Pattern QRSS. A 2
consecutive zero restriction.
Repetitive Pattern
Alternating Word Pattern
Modified 55 Octet (Daly) Pattern The Daly pattern is a
repeating 55 octet pattern that is byte aligned into the active
DS0 timeslots. The pattern is defined in a ATIS (Alliance
for Telecommunications Industry Solutions) Committee T1
Technical Report Number 25 (November 1993).
Reserved
IEOF
NAME AND DESCRIPTION
Change of Synchronization Status Interrupt Enable.
Interrupt enable for Synchronizer Status (BIR.0)
0 = interrupt masked
1 = interrupt enabled
Bit Error Detected Interrupt Enable. Interrupt enable for Bit
Error Detected (BIR.3)
0 = interrupt masked
1 = interrupt enabled
Bit & Error Counter Overflow Interrupt Enable. Interrupt
enable for the BERT Bit Counter (BIR.2) and BERT Error
Counter (BIR.1) overflow.
0 = interrupt masked
1 = interrupt enabled
Not Assigned. Should be set to 0 when written to.
Repetitive Pattern Length Bit 3 (RPL3). Refer to Table 15-2
for details.
Repetitive Pattern Length Bit 2 (RPL2). Refer to Table 15-2
for details.
Repetitive Pattern Length Bit 1 (RPL1). Refer to Table 15-2
for details.
Repetitive Pattern Length Bit 0 (RPL0). Refer to Table 15-2
for details.
–
Pattern Definition
89 of 157
RPL3
20
- 1 pattern with 14
RPL2
RPL1
(LSB)
RPL0
DS2196