DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 51

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

DS2196
7. STATUS AND INFORMATION REGISTERS
Found in each Framer/Formatter is a set of nine registers that contain information on the current real time
status of the DS2196, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1
to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller for the
FDL. BERT generator and receiver status is contained in the BERT Information Register (BIR). The
specific details on the registers pertaining to the BERT and FDL functions are covered in Section 15 and
18 but they operate the same as the other status registers in the DS2196 and this operation is described
below.
When a particular event has occurred (or is occurring), the appropriate bit in 1 of these nine registers will
be set to a 1. All of the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion.
This means that if an event or an alarm occurs and a bit is set to a 1 in any of the registers, it will remain
set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again (or in the case of the RBL, RYEL, LRCL or FRCL, and RLOS alarms, the bit
will remain set if the alarm is still present). There are bits in the four FDL status registers that are not
latched and these bits are listed in Section 18.
The user will always precede a read of any of the nine registers with a write. The byte written to the
register will inform the DS2196 which bits the user wishes to read and have cleared. The user will write
a byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit
positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location,
the read register will be updated with the latest information. When a 0 is written to a bit position, the read
register will not be updated and the previous value will be held. A write to the status and information
registers will be immediately followed by a read of the same register. The read result should be logically
AND’ed with the mask byte that was just written and this value should be written back into the same
register to insure that bit does indeed clear. This second write step is necessary because the alarms and
events in the status registers occur asynchronously in respect to their access via the parallel port. This
write–read– write scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS2196 with higher–order software languages.
The SR1, SR2, HSR and BIR registers have the unique ability to initiate a hardware interrupt via the INT
output pin. Each of the alarms and events in the SR1, SR2, HSR and BIR can be either masked or
unmasked from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2
(IMR2), HDLC Interrupt Mask Register (HIMR) and BERT Control Register (BC1) respectively. The
BC1 register is covered in Section 15. The HIMR register is covered in Section 18.
The interrupts caused by alarms in SR1 (namely RYEL, LRCL or RCL, RBL, and RLOS) act differently
than the interrupts caused by events in SR1 and SR2 (namely LUP, LDN, LSPARE, LOTC, RMF, TMF,
SEC, RFDL, TFDL, RMTCH, RAF, and LORC) and FIMR. The alarm caused interrupts will force the
INT pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the
set/clear criteria in Table 7–2). The INT pin will be allowed to return high (if no other interrupts are
present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still
present.
The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
ISR: INTERRUPT STATUS REGISTER (Address = 0E Hex)
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