DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 88

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

15.1 BERT REGISTER DESCRIPTION
BC0: BERT CONTROL REGISTER 0 (Address = 40 Hex)
(MSB)
SYMBOL
RESYNC
–
RINV
TINV
PS2
PS1
PS0
LC
–
TINV
POSITION
BC0.7
BC0.6
BC0.5
BC0.4
BC0.3
BC0.2
BC0.1
BC0.0
RINV
NAME AND DESCRIPTION
Not Assigned. Should be set to 0 when written to.
Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Pattern Select Bit 2. Refer to Table 15-1 for details.
Pattern Select Bit 1. Refer to Table 15-1 for details.
Pattern Select Bit 0. Refer to Table 15-1 for details.
Load Bit and Error Counters (LC). A low to high transition
latches the current bit and error counts into the host accessible
registers BBC0/BBC1/BBC2/BBC3 and BEC0/BEC1/BEC2
and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new
acquisition period. Must be cleared and set again for a
subsequent loads.
Force Resynchronization (RESYNC). A low to high
transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be
toggled from low to high whenever the host wishes to acquire
synchronization on a new pattern. Must be cleared and set
again for a subsequent resynchronization.
PS2
88 of 157
PS1
PS0
LC
RESYNC
(LSB)
DS2196