DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 128

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS2196 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS2196 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS2196. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Figure 20-3. Table 20-2 lists the device ID codes for
the DS2196.
Table 20-2: ID CODE STRUCTURE
Contents
Length
Instruction
MSB
(Contact Factory)
Version
4 bits
Boundary Scan
Bypass
Boundary Scan
Boundary Scan
Boundary Scan
Device Identification
Selected Register
(See Table 20-3)
Device ID
16 bits
128 of 157
“00010100001”
JEDEC
11 bits
Instruction Codes
010
111
000
011
100
001
1 bit
“1”
LSB
DS2196