AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 20

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

This circuit pulls SDMA4 low if M66EN is high during reset, indicating 66 MHz PCI operation. This
changes the default PCI hold time from “110” (2.9ns) to “000” (0.5 ns). This function fits easily in a PAL
such as the GAL22LV10, using the following equations:
DRV <= "00"
SDMA43_CFG <= DRV
It is also possible to provide the above adjustment in software if the code is able to determine the PCI bus
speed. It is not possible to sense the M66EN signal without external hardware (you cannot determine the
PCI bus speed from the HID1 PLL information, because those bits are an encoded version of the external
PLL settings). The system startup software may not be able to reliably access PCI devices until this is
change done, which can be a particular concern if the startup-software happens to be located on the PCI bus.
1.6.3 PCI Arbitration
While the MPC106 requires the use of an external PCI arbiter, a function typically provided by a “south
bridge” (such as the Winbond W83C553), the MPC107 includes a five-port PCI arbiter (not including
internal requesters such as the DMA engines and the core logic). MPC107 systems can directly control or
attach to the PCI bus without relying upon third-party chips.
Of course, if the PCI arbiter is not needed, it can be disabled and the MPC107 will act like any other PCI
requester.
1.7 Power
The MPC107 follows the trend of newer CMOS processes which in using low-core voltages to attain higher
operating speeds, unlike its single-voltage predecessor the MPC106. In addition, the MPC107 also divides
the I/O power pins of various signals into logical groups, each of which may be set to different voltages.
This allows the use of lower-voltage (faster) processor buses, allows clamping PCI signals to 5V if required
(dictated by the PCI bus), and allows the use of 2.5V or 3.3V memory signalling.
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to memory
HRESET
M66EN
Figure 13. Automatic PCI Hold Time Adjustment
MPC107 Design Guide
WHEN (M66EN = ‘1’)-- 66 MHz PCI
ELSE "11";-- 33 MHz PCI
WHEN (HRESET_B = ‘0’)-- Drive low during reset
ELSE "ZZ";-- otherwise float
2 K
Ω
2 K
Ω
SDMA3
SDMA4
MPC107