AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 25

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

As shown in Figure 18, this logic does not make use of the S_RST signal. This signal is asserted (for two
clock cycles) only when the EPIC is converted from parallel to serial mode, and is could be used to notify
external hardware to also convert from parallel to serial. Most systems will be fixed in one mode or the other,
so S_RST will not be used here.
Figure 19 shows the waveforms of the simple multiplexer. By using a negative-edge triggered clock (or
inverting the clock), the multiplexer can be reset to zero or advance to the next sample point in sufficient
time for the MPC107 to sample the S_INT pin on the rising edge of the clock. Since S_CLK is limited to
1/2 to 1/14th of the memory bus clock (effectively 7MHz to 50 MHz), this is well within the capabilities of
most modern FPGAs or PLDs.
Note that the reset signal must be synchronous; otherwise the clock-to-output timing of the MPC107 may
not be sufficient at higher speeds to guarantee that the Q counter resets to zero.
A sample of VHDL code which implements the serial multiplexer function follows:
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_1164.all;
INT15
S_INT sampled
INT0
S_FRAME
S_INT
S_CLK
Figure 18. MPC107 External Serial Multiplexer Block Diagram
Q(3:0)
Figure 19. MPC107 EPIC Interrupt Connections
16-to-1
mux
A(3:0)
XXXX
OUT
MPC107 Design Guide
Q(3:0)
4-bit counter
synchronous
0000
INT0
0001
CLR
INT1
0010
INT2
Interrupt Controller
S_CLK
S_FRAME
S_INT
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