AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 33

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

To simplify system design, the MPC107 also has the capability of asserting a reset signal (HRESET_CPU)
to the PowerPC processor, as shown in . In this configuration, the MPC107 asserts the processor HRESET
pin when the PCIRST# signal is asserted. The MPC107 will keep HRESET_CPU asserted for 2
bus clocks after its HRESET pin is released; this extra time allows the MPC107’s clock generator DLL and
the processor’s PLL to stabilize in sequence. After this additional time has elapsed, all clocks in the system
should be reliable and ready for reset to be released.
Since the HRESET_CPU pin is an open-drain output, it requires a weak pull-up (1K to 10K in value) to
provide a valid signal when not asserted. However, since it is open-drain, it can be “wire-OR” connected
(with no additional logic) with other optional reset signals, such as those from a COP debugger port, a
power-supply monitor, a watchdog timer, and a reset switch (assuming that the latter devices are also
open-drain).
1.10.1 Self-Reset
Using the EPIC (embedded programmable interrupt controller) it is possible for software to restart itself.
The usual connections from the EPIC to the processor allow it to assert the SRESET signal; this allows
software to restart cleanly but it does not force external hardware to initialize itself. If the software needs to
force a complete system initialization, it can use the SRESET signal in a different manner as shown in
Figure 27.
PCIRST#
+3.3V
+2.5V
HRESET
Reset & Power
COP Header
MPC107
Monitor
Figure 26. MPC107 Reset Logic
HRESET_CPU
COP_HRST
MPC107 Design Guide
RST
13
+3.3V
1KW
HRESET
MPC7400
17
processor
Reset
33