AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 9

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

1.4.5 Expanding Memory Clocks
Four clock are sufficient to directly drive two DIMM modules (two physical banks each), four registered
DIMMs (one clock per module), or four discrete SDRAM components. If this is insufficient, the memories
or modules must share clock signals; in such a case, the extra capacitive loading on the clock traces will
cause the time-of-flight (TOF) to be correspondingly longer. Using the feedback path, this effect can be
removed by lengthening the trace as described in Table 2. This longer feedback path will cause the SDRAM
clocks to “launch” earlier so that they will arrive along with the memory address and control signals.
If sharing is not sufficient, a clock regeneration device, also known as a zero-delay buffer, may be used to
replicate some of the clocks so that more are available, as shown in Figure 6.
SDRAM_SYNC_IN
SDRAS, SDCAS, CS
SDRAS, SDCAS, CS
SDRAM_CLK0
SDRAM_CLK0
sys_logic_clk
at SDRAM
at MPC107
at SDRAM
at SDRAM
at MPC107
at MPC107
DQx
DQx
0 ns
t
LOOP=1.0
t
OF=1.0
t
t
CTQ=5.5
CTQ=6.0
t
OF=1.0
Figure 5. Memory Timing for 100 MHz
5 ns
MPC107 Design Guide
t
t
OH=1.0
SU=3.5
t
SU=3
10 ns
Clocks
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