AN1849 Motorola / Freescale Semiconductor, AN1849 Datasheet - Page 4

• Manufacturer Part Number: AN1849
• Description: MPC107 Design Guide
• Manufacturer: Motorola / Freescale Semiconductor

should be designed so as to minimize the overall capacitive loading of the data bus. This might require, for
example, that large I/O system need buffering, or provide isolate address and control signal decoding in an
FPGA or PAL.
1.4 Clocks
A significant improvement offered by the MPC107 over previous solutions is the integration of a full
clocking system, which given a single PCI clock input, can synthesize all the clocks needed by a typical
embedded system:
In addition, the MPC107 includes a DLL adjustment that makes it easy to add or remove delay from memory
clock signals. This allows the designer to adjust the timing window of SDRAM signals to compensate for
heavily loaded systems, or to achieve PC100 compliance. The clock can be configured in many ways, but
most systems will use one of two architectures based upon whether the MPC107 is an agent or a host. It is
important to realize that the descriptions below reflect only the most widely used arrangements, many others
are certainly possible. The CPU and SDRAM clocks are independent of the PCI clock arrangement and will
be discussed separately.
1.4.1 Host Mode Clocking
When configured as a host, a typical system will use the PCI clock buffer to drive all PCI agents as well as
itself (with the PCI_SYNC_IN input). When the clocks are routed to equal lengths, the PCI requirements
regarding allowable clock skew are easily met, and all devices should be synchronized. Figure 2 shows an
example of a typical host-mode MPC107 system.
4
•
•
•
•
2 processor bus clocks
1 local bus slave clock
4 memory bus clocks
5 PCI bus clocks
33 MHz
OSC
PCISYNC_IN
OSC_IN
MPC107
Figure 2. Host Clock Architecture
MPC107 Design Guide
SDRAM_CLK3
SDRAM_CLK0
CPUCLK0
CPU_CLK(0:1)
CPU_CLK(2)
SDRAM_CLK(0:3)
PCI_CLK(0:4)
feedback
MPC7400
SDRAM
PCI DEVICE
PCI DEVICE
PCI DEVICE
system
rest of