AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 14

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor, Inc.
Application Note
After initializing the FCLKDIV register with the proper value, the PPAGE
register and the BKSEL[1:0] bits must be initialized. The PPAGE register
must be written with a value that places the correct 16-K memory block
in the PPAGE window that contains the memory area to be erased. If a
mass (bulk) erase operation is performed on one of the 64-K blocks, the
PPAGE register may be written with any one of the four PPAGE values
associated with a 64-K block. Note that when performing a mass or
sector erase in the address range of one of the two fixed pages,
$4000–$7FFF or $C000–$FFFF, the value of the PPAGE register is
unimportant.
The BKSEL[1:0] bits, located in the FCNFG register, are used to select
the banked status and control registers associated with the 64-K FLASH
block in which the erase operation is to be performed. As shown in
Figure
1, the value of the FLASH block number decreases with
increasing PPAGE values. Closely examining
Figure 1
reveals that the
correct value for the BKSEL[1:0] bits is the one’s complement of the
PPAGE[3:2] register bits. Even though the flowchart shows the block
select bits being written before the PPAGE register, these registers may
be written in reverse order. This makes the code implementation straight
forward since the value of the block select bits may be easily derived
from the value written to the PPAGE register.
After initializing the PPAGE register and the block select bits, the
command buffer empty interrupt flag (CBEIF) bit should be checked to
ensure that the address, data and command buffers are empty. If the
CBEIF bit is set, the buffers are empty and a program or erase command
sequence can be started. The next three steps in the flowchart must be
strictly adhered to. Any intermediate writes to the FLASH control and
status registers or reads of the FLASH block on which the operation is
being performed will cause the access error (ACCERR) flag to be set
and the operation will be immediately terminated. For a mass erase
operation, the address of the aligned data word may be any valid
address in the 64-K block. For a sector erase, only the upper seven
address bits are significant, the lower eight bits are ignored. For all erase
operations, the data written to the FLASH block is ignored.
AN2153
14
MOTOROLA
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