AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 5

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

FLASH Protection
AN2153
MOTOROLA
Unbanked
Reserved
Reserved
FCLKDIV
FCNFG
Banked
FPROT
FSTAT
FCMD
FSEC
FPOPEN
FDIVLD
KEYEN
CBEIE
CBEIF
Bit 7
0
0
0
PRDIV8
ERASE
Figure 2. FLASH Status and Control Registers
CCIE
CCIF
NV6
The protected areas of each FLASH block are controlled by four bytes
of FLASH memory residing in the fixed page memory area from
$FF0A–$FF0D. During the microcontroller reset sequence, each of the
four banked FLASH protection registers (FPROT) is loaded from values
programmed into these memory locations. As shown in
location $FF0A controls protection for block three, $FF0B controls
protection for block two, $FF0C controls protection for block one, and
$FF0D controls protection for block zero.
The values loaded into each FPROT register determine whether the
entire block or just subsections are protected from being accidentally
erased or programmed. As mentioned previously, each 64-K block can
have two protected areas. One of these areas, known as the lower
protected block, grows from the middle of the 64-K block upward. The
other, known as the upper protected block, grows from the top of the
64-K block downward. In general, the upper protected area of FLASH
block zero is used to hold bootloader code since it contains the reset and
interrupt vectors. The lower protected area of block zero and the
protected areas of the other FLASH blocks can be used for critical
parameters that would not change when program firmware was updated.
6
0
F
0
Freescale Semiconductor, Inc.
For More Information On This Product,
KEYACC
FPHDIS
FDIV5
PVIOL
PROG
NV5
5
0
0
Go to: www.freescale.com
ACCERR
FPHS1
FDIV4
NV4
4
0
0
0
0
FPHS0
FDIV3
NV3
3
0
0
0
0
0
FPLDIS
ERVER
BLANK
FDIV2
Overview of the MC9S12DP256’s FLASH
NV2
2
0
0
0
BKSEL1
SEC01
FPLS1
FDIV1
1
0
0
0
0
BKSEL1
SEC00
FPLS0
FDIV0
MASS
Bit 0
Figure
0
0
0
Application Note
3,
$x100
$x101
$x102
$X103
$X104
$X105
$X106
$X107–
$x10F
5