AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 15

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

FLASH
Programming
AN2153
MOTOROLA
After writing a program or erase command to the FCMD register, the
CBEIF bit must be written with a value of 1 to clear the CBEIF bit and
initiate the command. After clearing the CBEIF bit, the ACCERR and
PVIOL bits should be checked to ensure that the command sequence
was valid. If either of these bits is set, it indicates that an erroneous
command sequence was issued and the command sequence will be
immediately terminated. Note that if either or both of the ACCERR and
PVIOL bits are set, they must be cleared by writing a 1 to each flag’s
associated bit position before another command sequence can be
initiated. Five bus cycles after the CBEIF bit is cleared, the CCIF flag will
be cleared by the state machine indicating that the command was
successfully begun. If a previous command has not been issued, the
CBEIF bit will become set, indicating that the address, data, and
command buffers are available to begin a new command sequence.
Once the erase command has completed, erasure of the sector or block
should be verified to ensure that all locations contain $FF. When erasing
a 512-byte sector, each byte or word must be checked for an erased
condition using software. Fortunately, however, the state machine has a
verify command built into the hardware to perform an erase verify on the
contents of any of the 64-K blocks. The command sequence used to
perform an erase verify is identical to that of performing an erase
command except that the erase verify command ($05) is written to the
FCMD register and the block select bits and the PPAGE register need
not be rewritten. If all locations in a 64-K block are erased, a successful
erase verify will cause the BLANK bit in the FSTAT register to be set.
Note that the BLANK bit must be cleared by writing a 1 to its associated
bit position before the next erase verify command is issued.
As mentioned in the previous section, the erase and program operations
follow a nearly identical flow. There are, however, some minor changes
to the flow that can improve the efficiency of the programming process.
To take advantage of the decreased programming time provided by the
2-stage FIFO command buffer, it must be kept full with programming
commands. As the flowchart in
each programming command to complete, a new programming
command is issued as soon as the CBIEF flag is set. This allows the
programming voltage to remain applied to the array as long as the next
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Figure 9
Overview of the MC9S12DP256’s FLASH
shows, rather than waiting for
Application Note
15