AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 25

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

AN2153
MOTOROLA
a P cycle to maintain queue order. If the first byte is aligned (at an even
address), the O cycle is an f cycle. Consequently, if the first byte of the
STAB instruction using extended addressing is aligned to an even byte
boundary, the O cycle will be an f cycle. This will then provide the cycle
of delay required while the RAM is overlaying the FLASH. Because the
default address of the INITRM register is in the direct page addressing
range, most assemblers will use direct rather than extended addressing.
The greater than character (>) appearing as the first character in the
operand field of the STAB instruction is used to force extended
addressing. Note that some assemblers may not recognize this modifier
character.
The main reason for relocating the RAM, rather than executing the
bootloader at the RAM’s default address, is to allow the SCI0 interrupt
vector to be changed. Because the on-chip RAM has a higher priority in
the memory decoding logic than the on-chip FLASH, overlaying the
FLASH with the on-chip RAM causes the RAM to be accessed rather
than the FLASH. Due to the fact that the bootloader’s communications
routines utilize the SCI in a buffered, interrupt driven mode, the SCI0
interrupt vector must be initialized to point to the bootloader’s SCI
interrupt service routine.
After relocating the on-chip RAM, the startup code initializes the PLL and
engages it as the bus clock. The values for the REFDV and SYNR
registers are calculated by the assembler based on values of the
oscillator frequency (OscClk), final bus frequency (fEclock), and the
desired reference frequency (RefClock). In this case, the final bus
frequency is specified to be 24.0 MHz. Because this is an integer
multiple of the oscillator frequency, the oscillator frequency can be used
as the reference clock for the PLL. This results in a value of zero being
written to the REFDV register. To obtain a bus clock of 24 MHz, the
reference frequency must be multiplied by three. The value written to the
SYNR register multiplies the reference clock by SYNR+1 to generate the
bus clock. Therefore, a value of two is written to the SYNR register to
obtain a 24-MHz bus clock. Note that the four NOP instructions following
the STAB instruction work around a bug in the 0K36N mask set. This
errata manifested itself in the LOCK bit not being cleared until several bus
cycles after a write to the SYNR register had occurred. Also note that a
24-MHz bus clock was chosen to support a baud rate of 115,200.
Freescale Semiconductor, Inc.
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Bootloader Software
Application Note
25