AN2153 Freescale Semiconductor / Motorola, AN2153 Datasheet - Page 29

• Manufacturer Part Number: AN2153
• Description: A Serial Bootloader for Reprogramming the MC9S12DP256 FLASH Memory
• Manufacturer: Freescale Semiconductor / Motorola

AN2153
MOTOROLA
The ProgFBlock subroutine performs the task of programming the
received S-record data into the on-chip FLASH. While the subroutine
generally follows the flowchart in
rearranged to improve the efficiency of the implementation. The first two
steps in the flowchart, writing the PPAGE register and block select bits,
are performed in the ProgFlash subroutine. Note that the order of
these two operations is not important. Because the value for the block
select bits is derived from the PPAGE value, the ProgFlash subroutine
writes the PPAGE register value first.
The third operation in the flowchart checks the state of the CBEIF bit to
ensure that the command buffer is empty and ready to accept a new
command. This check is not made at the beginning of the ProgFBlock
subroutine because the bit is known to be set when the subroutine
completes execution. This condition is inferred by the fact that the CCIF
flag is set before the programmed data from the previously received
S-record is verified.
The ProgFBlock subroutine begins by retrieving the S-record
code/data field length, dividing the value by two and placing the result on
the stack. The code/data field length is divided by two because the
FLASH is programmed a word at a time. Next, the X and Y index
registers are initialized to point to the FLASH and S-record data
respectively. Note that the X index register is loaded with the value in the
PPAGEAddr global variable. This value, calculated using the second
formula in
initializing the pointers, the programming loop is entered at label
ProgLoop. Note that within the programming loop there are no
instructions that directly correspond to the five bus cycle delay before
checking the state of the CBEIF flag after issuing the program
command. Instead, the five bus cycle delay is inherent in the three
instructions (LDAB, BITB, BNE) used to check the state of the ACCERR
and PVIOL status bits. This loop follows the remainder of the flowchart
in
flag is set until all of the count in the local variable NumWords is zero.
Before verifying that all of the FLASH locations programmed properly,
the firmware must wait until the CCIF flag is set, indicating that all issued
programming commands have completed. Failure to observe this
Figure
Freescale Semiconductor, Inc.
For More Information On This Product,
9, issuing a new programming command each time the CBEIF
Figure
Go to: www.freescale.com
11, will always point within the PPAGE window. After
Figure
9, some operations have been
Bootloader Software
Application Note
29