AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet
AN2434
Related parts for AN2434
AN2434 Summary of contents
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... Provides some background and insight into the pin drivers and related structures • Provides a process for evaluating source and sink currents • Interprets the data of the evaluation in a graphic comparison to factory specifications © Freescale Semiconductor, Inc., 2004. All rights reserved. AN2434 Rev. 0, 9/2004 ...
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Pin Logic Structure Pin Logic Structure The logic structure for a general-purpose input/output (GPIO) pin is illustrated in includes: • Output driver • Input buffer • Pullup and pulldown sources • Electrostatic discharge (ESD) protection • Input hysteresis • Level ...
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The simplified illustration of an output driver in provide a current path between the output pin and both V the p-channel FET is enabled. To drive the pin low, the n-channel FET is enabled. There is also a series resistor ...
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Unique Pins of the ports associated with the core are available for use as general-purpose input/output (GPIO) in the non-expanded modes. Because these ports are part of the core, their capabilities are grouped differently than the PIM ports. For example, ...
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Pins that may be used as input/output should be terminated individually to permit maximum flexibility if they are needed later in the design process. Pins that are configurable as ...
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ESD Structures ESD Structures The ESD structure generally consists of diodes from the signal pins to the power and ground rail. These diodes are reverse biased with respect to the rails and serve to clamp external voltages to no more ...
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Injection Current When the applied voltage or an input pin rises above V According to the device electrical specification for the 9S12DP256, injected currents should be limited to ±2.5 mA for any single pin. Injection currents above this specification can ...
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Input Characteristics Input Characteristics Specifying the input levels as 65% and 35 65 above, it will be recognized as a logic-high level. When a voltage falls to 35 below, it will be ...
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Pullup Current The pullup current was measured by a current meter in series between the input pin and a variable power supply. With the power supply set to 5.0 Vdc, there is a slight leakage current into the input pin. ...
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Source and Sink for Full-Drive Currents current are shown in Figure 8 and (GPIO) pin is shown. The GPIO pins are contained in two sections of the MCU: • Core • Port integration module (PIM) The core includes ports A, ...
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SPECIFIED I OH 3.5 3 2.5 2 1 Figure 8. V The current that an output pin can sink is measured by connecting the output pin via a resistor to V driving the output pin ...
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Source and Sink for Full-Drive Currents SPECIFIED I OL 3.5 3 2.5 2 1 Figure 10 +25 mA INSTANTANEOUS MAXIMUM RECOMMENDED CURRENT FOR DIGITAL OUTPUT PINS (mA) OL versus Sink ...
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Source and Sink for Reduced Drive HCS12 I/O pins include a reduced current mode. This mode is provided to reduce EMI emissions in cases where the load being driven by the I/O pins is light and full drive strength is ...
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Capacitive Loading SPECIFIED I OL 3.5 3 2.5 2 1 Figure 12. V Capacitive Loading Device electrical 7specifications typically show parameters such as V maximum electrical signal levels and timing criteria based on a specified loading ...
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Figure 13. Effect of Long Leads and Stray (or Parasitic) Impedances By minimizing the length of component leads, PCB traces, and wire used to connect the scope probe, many of these effects can be reduced. and 470 pF with very ...
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Capacitive Loading 0 pF LOAD 1.67 ns RISE TIME 200 pF LOAD 22.25 ns RISE TIME 470 pF LOAD 50.55 ns RISE TIME Figure 14. Rise Times under Different Loads (Rise Times Were Measured from 20% to 80%) 16 Input/Output ...
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Inductive Loading When driving a load such as an inductor or capacitor that might result in voltages beyond one should take care to provide external circuitry (such as Schottky diodes), which will protect both SS the MCU ...
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Conclusion Conclusion The graphs and data in this application note suggest that MCU GPIO pins can source or sink much more current than the official specification recommends. Though adverse effects may not be immediately apparent, the damaging phenomena described in ...
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Glossary ATD — analog-to-digital converter CMOS — complementary metal oxide semiconductor EMF — electro-motive force ESD — electrostatic discharge FET — field effect transistor GPIO — general-purpose input/output Hysteresis — A function which lags or falls behind. Generally a function ...
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Appendix A High Performance Embedded Systems Division Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Failure Analysis Technical Report on Electrical Overstress (EOS) What is EOS? 1 Electrical overstress (EOS) is the misapplication of excessive voltage ...
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High Performance Embedded Systems Division Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Failure Analysis Technical Report on Electrical Overstress (EOS) Typical Failure Mechanisms for EOS The physical failure mechanism which results from an EOS event ...
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Appendix B Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer What is ESD? Electrostatic Discharge is the application of a short duration high energy pulse to the ...
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Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer + + + + + + + + + ZAP ...
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Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer + + + + + + + + + + + + + + ZAP! GROUND ...
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Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer four main failure mechanisms (discussed later) Occasionally, high supply current and even functional failures can be seen on ESD ...
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Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer Contact damage , also called contact spiking, is the result of this particular phenomena. See Figure 5. When the ...
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Reliability and Quality Assurance 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Electrostatic Discharge (ESD) in Integrated Circuits - A Primer Figure 6 - SEM micrograph of poly melt filaments. The unit has been stripped back to reveal Figure 7 ...
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... Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com AN2434 Rev. 0, 9/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...