AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet - Page 25

• Manufacturer Part Number: AN2434
• Description: Input/Output (I/O) Pin Drivers
• Manufacturer: Freescale Semiconductor / Motorola

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Electrostatic Discharge (ESD) in Integrated Circuits - A Primer
four main failure mechanisms (discussed later)
Occasionally, high supply current and even functional failures can be seen on ESD failures.
What a re typical ESD failure mechanisms?
As mentioned earlier, there are four main failure mechanisms associated with ESD events.
They are junction degradation, thermal oxide degradation, poly melt filaments and contact
damage. All are the direct result of localized heating caused by excessive current.
important to understand the configuration of the output buffers, and their role in the ESD event.
Figure 4 shows a cross section through an I/O pad and output buffers.
The high energy pulse which is absorbed by a pin travels through the pn junctions attached t o
the pad, which are the drains of the output n-channel and p-channel transistors for that pin. A s
is typical in an ESD event, the voltage applied to the pad exceeds the reverse bias breakdown
voltage of the drain junctions. Impact ionization causes high current to flow through the diode.
The current (and heat generated) eventually becomes localized due to some non-uniformity in
the junction processing or the device layout (i.e. the contact closest to the energy source).
This increase in temperature increases the intrinsic
resistance along that current path. This becomes a preferential current site.
flows
resistance, allowing more current to flow, and so on ... a positive feedback system.
Figure 3 - Schematic of a typical I/O pin and the curve traces of various failure modes.
n+
Figure 4 - Diagram of a cross-section through an I/O pad, showing output buffers.
here,
VDD
p+
Drivers
Outpu t
generating more heat, lowering
transistor
p-ch
VDD
VSS
n- well
p+
I/O
Pad
Input
I/O pad
Meta l
Oxid e
Pol y
the intrinsic
can
short
I
carrier
cause any of these failure
resistive
leaky
(VDD)
n+
concentration,
concentration, lowering the
leaky
(VSS)
transistor
n-ch
VDD
(rev 2.0 - 5/5/95)
good
n+
More current
reducing
V
VSS
p- substrate
p+
modes.
It i s
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the