AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet - Page 20

• Manufacturer Part Number: AN2434
• Description: Input/Output (I/O) Pin Drivers
• Manufacturer: Freescale Semiconductor / Motorola

Appendix A
High Performance Embedded Systems Division
Reliability and Quality Assurance
6501 Wm. Cannon Drive West
Austin, Texas 78735-8598
Failure Analysis Technical Report on Electrical Overstress (EOS)
What is EOS? 1
Electrical overstress (EOS) is the misapplication of excessive voltage or current to the external leads
of an integrated circuit. The damage caused by EOS is actually a result of the total energy applied to
the device. Externally, the damage will result in open, short or leaking pins. It can also affect the
devices functionality. Internally, the result is typically seen as fused bond wires or damage to the die
metalization.
EOS vs. ESD
The key difference between EOS and electrostatic discharge (ESD) is the rise time of the energy pulse.
Rise times associated with an ESD event are in the 5-20 ns range while the rise times for EOS events
tend to be much longer. Failure mechanisms associated with both types of events are strictly due to
localized heating. Where the localized heating occurs is key understanding the failure mechanisms.
Damage seen on bond wires and die metalization are typically associated with EOS (slow rise time, high
energy) while junction degradation, poly melt filaments and contact damage are associated with ESD
(fast rise time, high energy). Typically, most ESD damage is only visible through deprocessing and
SEM inspection. Most EOS damage is visible through an optical microscope.
Typical Failure Modes for EOS
The most common failure modes indicating an EOS event are open pins, shorted pins and leaking pins.
Figure 1 shows the curve traces for each of these situations on a standard I/O pin. Open pins are the
result of bond wires or die metalization which has been vaporized and has fused open. Shorted and
resistive pins are usually due to die metalization and oxide melting then reflowing into adjacent
metal. Leaky pins can also be due to the reflowing of metal and oxide in and near active areas.
1 This technical report was compiled by Carole LeClair of Motorola's CSIC Failure Analysis Lab.
Figure 1.
associated with the pin.
VSS
VDD
I/O
Schematic for a typical I/O pin and the
VSS
i/p
resistive
open
short(Vss)
good
I
curve traces which could be
short(Vdd)
leaky
good
V
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