AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet - Page 2

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AN2434

Manufacturer Part Number
AN2434
Description
Input/Output (I/O) Pin Drivers
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Pin Logic Structure
Pin Logic Structure
The logic structure for a general-purpose input/output (GPIO) pin is illustrated in
includes:
2
Output driver
Input buffer
Pullup and pulldown sources
Electrostatic discharge (ESD) protection
Input hysteresis
Level shifter
Control logic
Note that the pulldown structure is generally not present on the core
register pins — the 9S12H Family is an exception. The level shifter provides
2.5-V to 5.0-V level translation. The ESD protection will be discussed briefly
in
control the various pin modes.
ESD
PAD
Structures. The control logic is used by the MCU to enable and
V
V
DDX
SSX
Figure 1. Logic Structure for a GPIO Pin
ESD
WEAK PULL DOWN
WEAK PULL UP
Input/Output (I/O) Pin Drivers, Rev. 0
OUTPUT
DRIVER
BUFFER
INPUT
NOTE
PREDRIVER
SHIFTER
LEVEL
LOGIC
Figure
Freescale Semiconductor
1. The structure

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