AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet - Page 24

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AN2434

Manufacturer Part Number
AN2434
Description
Input/Output (I/O) Pin Drivers
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Reliability and Quality Assurance
6501 Wm. Cannon Drive West
Austin, Texas 78735-8598
Electrostatic Discharge (ESD) in Integrated Circuits - A Primer
What is Motorola's ESD Qualification Criteria?
Before any Motorola CSIC microcontroller
demonstrate the ability to withstand repeated 2000V HBM and 200V MM stresses on all I / O
pins. Each I/O pin is zapped with respect to every other pin on the chip. For example, on a 4 4 -
pin device, an I/O pin will need to be zapped 43 times, once to each of the other pins. If the
device passes to the production test program following this ESD stressing, it is said to have
passed ESD testing.
There is currently no specification regarding CDM susceptibility.
cooperation with IEEE, is in the process of developing a standard for component level ESD
sensitivity
complete, it will allow standardized testing of CDM ESD.
What are typical ESD failure modes?
Usually, a device which has failed to withstand an ESD event will have leaky or shorted pins.
Because the stress enters the device through the pad, it stands to reason that the circuitry in
closest proximity to this stress will fail first.
and the curve traces for various types of pin failure modes. It is important to note that the
+
+
+
+
+
+
+
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testing.
+
+
+
+
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ZAP!
Figure 2 - Charged Device Model (CDM) stressing.
The standard (#DS5.3-1993)
C
u
r
r
e
n
t
0
GROUND
Time (nanoseconds)
with a 500V CDM event
Peak current is 7.5A
on a 4pF device
1
Voltage
Supply
High
Figure 3 shows a typical I/O pad configuration,
achieves "MC"
Charging
Resistor
CDM Equivalent Circuit
is currently
2
Charge
Switch
Device Under Test
(production)
Discharge
GROUND
in "draft"
Switch
The ESD Association, in
(rev 2.0 - 5/5/95)
status,
status.
it
must
Once
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