AN2434 Freescale Semiconductor / Motorola, AN2434 Datasheet - Page 26

• Manufacturer Part Number: AN2434
• Description: Input/Output (I/O) Pin Drivers
• Manufacturer: Freescale Semiconductor / Motorola

Reliability and Quality Assurance
Page 5 of 6
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Electrostatic Discharge (ESD) in Integrated Circuits - A Primer
(rev 2.0 - 5/5/95)
Contact damage , also called contact spiking, is the result of this particular phenomena. See
Figure 5. When the excessive current causes the aluminum to heat beyond its melting point o f
660C, the aluminum, which is positively charged, drifts into the substrate under the influence
of the electric field.
Eventually, the aluminum dopant reaches through the drain diffusion and
into the substrate, shorting the drain/substrate diode, and resulting in a pad-Vss leakage path.
Junction damage can also occur in this scenario. If the heat generated by this localized current
flow exceeds the melting point of silicon (1400 ° C), the silicon will melt and reflow, disrupting
the dopant profiles in this region of the pn junction.
When the ESD event is over, the silicon
recrystallizes, with the n and p-type dopants mixed up, resulting in poor isolation between p -
and n- type regions, and a leaky drain/substrate diode. This type of damage is only visible
after a decoration etch is performed to highlight areas of damaged silicon.
This failure
mechanism is usually accompanied by other more visible mechanisms, such as contact spiking.
I/O pad
VSS
n+
n+
p+
n-ch
transistor
Aluminum
p- substrate
Spike
Figure 5 - Diagram of contact spiking.
Thermal oxide degradation and poly melt filaments are closely related failure mechanisms.
Localized heating of a source/drain region can degrade the integrity of the gate oxide in the
vicinity to the point of breakdown, causing a gate oxide short. If the heat generated by the high
current flow from the polysilicon gate to the source/drain region reaches the melting point o f
silicon, then silicon from the s/d region migrates towards the gate. A "trench" is left in the
junction where the silicon has been evacuated. Figure 6 is a SEM micrograph a device which
has been deprocessed down to polysilicon to reveal these poly melt filaments, or "tree roots".
As mentioned earlier, more than one failure mechanism can be present on an ESD failure.
The
SEM micrograph in Figure 7 shows several mechanisms which occurred as the result of a single
ESD event. The unit in this case has been stripped back to silicon.
A spiked contact, poly melt
filament "trench" and gate oxide rupture are all present.