AN2727 Freescale Semiconductor / Motorola, AN2727 Datasheet

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AN2727

Manufacturer Part Number
AN2727
Description
Designing Hardware for the HCS12 D-Family
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Freescale Semiconductor
Application Note
Designing Hardware for the
HCS12 D-Family
by: Martyn Gallop
Introduction
This document contains hardware guidelines for designing with the HCS12 D-family of microcontrollers
from Freescale Semiconductor. This includes:
© Freescale Semiconductor, Inc., 2004. All rights reserved.
Applications Engineering
Freescale Semiconductor,
East Kilbride
Pinout overview
Power supply connections
Control pin connections
I/O connections
Electrical parameters mentioned in this document are subject to change in
individual device specifications. Check each application against the latest
data sheet for specific target devices.
NOTE
Rev. 0, 12/2004
AN2727

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AN2727 Summary of contents

Page 1

... Control pin connections • I/O connections Electrical parameters mentioned in this document are subject to change in individual device specifications. Check each application against the latest data sheet for specific target devices. © Freescale Semiconductor, Inc., 2004. All rights reserved. NOTE AN2727 Rev. 0, 12/2004 ...

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Recommended Documentation Recommended Documentation Other documentation useful for HCS12 D-family hardware design can be found on the external Freescale web site (http://www.freescale.com): Specific Device User Guide. The specific device Voltage Regulator Block User Guide. The Specific device Port Integration Block ...

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Byte Flash EEPROM 2K - 14K Byte RAM Byte EEPROM VDDR VSSR Voltage Regulator VREGEN VDD1,2 VSS1,2 Single-wire Background BKGD Debug Module XFC Clock and VDDPLL Reset PLL VSSPLL Generation EXTAL Module XTAL RESET ...

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Pin States Following Reset in Normal Single Chip Mode Pin States Following Reset in Normal Single Chip Mode Typically, I/O pins are configured as inputs following a reset; this is done to avoid conflict with application signals driving I/O pins. ...

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PP3 1 PP2 2 PP1 3 PP0 4 PK3 5 PK2 6 PK1 7 PK0 8 PT0 9 PT1 10 PT2 11 PT3 12 VDD1 13 VSS1 14 PT4 15 PT5 16 PT6 17 PT7 18 PK5 19 PK4 20 ...

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Pin States Following Reset in Normal Single Chip Mode PP3 PP2 PP1 PP0 PT0 PT1 PT2 PT3 VDD1 VSS1 PT4 PT5 PT6 PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 = Input, high impedance = Input, internal pull-up enabled = Analog ...

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Power Supply Considerations There are two power supply voltages: • 2.5V supply for logic, the CPU core, PLL, and oscillator, • 5V supply (VDD5) for the I/O buffers, voltage regulator, and ATD. In some cases, the different supplies may be ...

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HCS12 Power Supplies HCS12 Power Supplies Vdd1, Vdd2 2.5V supply for MCU core and peripheral logic. If using the internal regulator, connect only to external decoupling capacitors. Vddpll 2.5V supply for oscillator and PLL. If using the internal regulator, connect ...

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In extreme cases, where high frequency system noise is present, low ESR beads may be necessary on VRH. Series resistance should be avoided, as each ATD reference draws ~375 µA from the reference supply (VRH=5V). Ground The oscillator return should ...

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Pin Considerations Collection – Control Pin Considerations Collection – Control There are several control pins on the device that require special consideration at the design stage: TEST Pin This pin should always be grounded in an application. This is a ...

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Take care reading the documentation when determining the polarity of the XCLKS pin possible for different HCS12 families to have alternative polarity on this pin for oscillator selection. The block user guide for the oscillator refers to the ...

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... Internally, it has a permanently enabled weak pull-up, to ensure that it enters normal mode if not connected. This pull-up may not be strong enough to ensure adequate rise times for BDM communication with all development tools. If BDM support is required it is recommended to fit an external pull-up resistor. See Easy access to the RESET, BKGD, 0V and VDD5 signals can facilitate debugging ...

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Implementing a Standard Serial Debug Interface for the Background Debug Module (BDM) Implementing a Standard Serial Debug Interface for the Background Debug Module (BDM) The BDM module is a single-wire debug interface supported on HCS12 MCUs. Bidirectional communication is via ...

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HCS12 PLL HCS12 PLL PLL Filter Circuit The HCS12 PLL allows programmable bus frequencies to be generated from the oscillator clock. With the PLL disabled: ECLK (bus) freq With the PLL enabled: ECLK (bus) freq The PLL on the HCS12 ...

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Oscillator Options On the HCS12 D-family there are three oscillator options: • Low power, amplitude controlled Colpitts configuration. • Full swing (2.5V) Pierce configuration (not available on MC9S12D256x K36N and K79X masks). • External clock source – Uses the same ...

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Oscillator Options Start-up time and margin are typical values, measured on carefully laid out PCBs. The current values have been simulated for typical conditions. The use of a fundamental resonator or crystal is always recommended in preference to an overtone ...

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If a PCB is designed to allow both external circuit configurations, it should be optimized for Colpitts mode. These guidelines are valid for single sided, double sided, and multi-layer boards. On boards with multiple layers, it may be possible to ...

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S12 CRG — Pierce Oscillator S12 CRG — Pierce Oscillator 500 kHz to 40 MHz crystal / resonator (not available on MC9S12D256x K36N and K79X masks). On the D-family, pull XCLKS pin low at reset. This is also the configuration ...

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S12 Pierce Oscillator Layout Example Designing Hardware for the HCS12 D-Family, Rev. 0 Freescale Semiconductor S12 CRG — Pierce Oscillator 19 ...

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S12 CRG — Colpitts Oscillator S12 CRG — Colpitts Oscillator 500 kHz to 16 MHz low power oscillator pk-pk with DC offset. On the D-family, pull XCLKS pin high at reset. MCU * Possible d.c. blocking capacitor (C ...

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S12 Colpitts Oscillator Layout Example Designing Hardware for the HCS12 D-Family, Rev. 0 Freescale Semiconductor S12 CRG — Colpitts Oscillator 21 ...

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Pin Considerations — General Purpose I/O Pin Considerations — General Purpose I/O The functionality of each pin is described in the appropriate device user guide. The detailed functionality of the GPIO is described in the appropriate Port Integration Module (PIM) ...

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HCS12 Core I/O Ports Ports A, B and K can be used as GPIO. In expanded modes these ports form the expanded address and data bus. Registers for these ports are located in HCS12 core. Much of Port E can ...

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Pin Considerations — General Purpose I/O digital data output stream, unless the reference potential is sensed at the reference input pin and any potential drop compensated for. Due to the sample-and-hold mechanism of the HCS12 ATD, charge-sharing between the external ...

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A useful feature of the PIM is that when an interrupt is enabled on one of the ports the appropriate pull device for the selected edge polarity is enabled: • falling edge = pull-up enabled • rising edge = pull-down ...

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MC9S12DP256 MODRR Routing options MC9S12DP256 MODRR Routing options The PIM module on the D-family can re-route the I/O connectivity for a number of communications peripherals depending on the value contained in the Module Routing Register (MODRR). This is primarily intended ...

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Managing Unused Pins If a general purpose input does not have a pull device enabled or is not driven externally, as the input approaches mid-rail (i.e. ~ 2.5 V), a ‘cross-over current’ 2.5 mA can flow in the ...

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Output Drive Currents or • a port is connected directly to a supply rail and might be driven to the opposite polarity from the supply rail. In either case, the maximum IDD specification for the pin will be exceeded, and ...

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When driving high impedance loads such as logic devices the voltage dropped across the output RDSON will be low, and the VOH and VOL levels will be much closer to the appropriate supply rail voltages. I/O Injection Currents All digital ...

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Connecting Capacitors Directly to Output Pins channels (coupling ratio K), generating an error voltage proportional to the source resistance of the input being converted. The additional input voltage error on the converted channel can be calculated as V with I ...

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With the exception of the D32, the 80-pin variant uses the same die as the 112-pin variant. This is not a direct consideration at the hardware design stage as such; however, the application software must configure undefined inputs on port ...

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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com AN2727 Rev. 0, 12/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...

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