AN2727 Freescale Semiconductor / Motorola, AN2727 Datasheet - Page 13

• Manufacturer Part Number: AN2727
• Description: Designing Hardware for the HCS12 D-Family
• Manufacturer: Freescale Semiconductor / Motorola

Implementing a Standard Serial Debug Interface for the Background Debug Module (BDM)
The BDM module is a single-wire debug interface supported on HCS12 MCUs. Bidirectional
communication is via a single pin on the MCU (the BKGD pin). Typically, a BDM interface cable will
connect to four signals: BKGD, RESET, VSS, and VDD5.
Standard Serial Debug Interface Connection
Although a debug cable may derive power from a source other than the target board, the target VDD5
and GND signals may be required with some cables to provide a reference level for the cable’s I/O buffers,
so routing these supplies to the connector is always recommended.
BKGD Pull-up Value
The MCU BDM module generates ‘speed up’ pulses, so the value of the pull-up is almost irrelevant from
the point of view of the MCU, and the specific value of the pull-up required on the BKGD pin is really a
debug tool consideration rather than an MCU one.
By default, the BDM module is clocked from the external oscillator clock (EXTAL); however, some BDM
programming utilities may select the PLL as the clock source for the BDM.
Aim for t = R*C of about 20% of the maximum BDM speed with the BDM speed = 1/16 of the maximum
expected BDM module clock.
So, for a 25 MHz bus => 1 µs bit time => at 100 pF (nominal load) => R = 200 ns / 100 ps = 2 k
This simplifies to R = 32 x 10
Although a low impedance may not be necessary for communication at the application’s target bus speed,
using a lower impedance value may be advantageous in electrically noisy environments. However, the
resistor value should always be >> ~ 600
The drive capability of the BDM tool used must also be considered — it must be able to drive the selected
resistor and line capacitance low. Check any concerns with the BDM cable supplier.
Freescale Semiconductor
BDM tool can be RS-232, LPT, Ethernet, or USB interface
0.023” square posts
0.100” spacing
Implementing a Standard Serial Debug Interface for the Background Debug Module (BDM)
Vdd (pin 6) is optional to power the BDM tool
9
Designing Hardware for the HCS12 D-Family, Rev. 0
/ BDM module clock frequency. For example, for 16 MHz, R = 2 k
Figure 3. Connector Pinout
Ω,
to ensure that a low state will be detected.
BKGD 1
Top view
3
5
2 VSS
4 RESET
6 VDD5
Ω
Ω
.
.
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